[gem5-users] L2 or L3 cache interface

[Fengze Yu via gem5-users]

Hi 


What is the interface between L1 and L2 cache in Ruby cache coherence model? Is 
there a clear defined interface, similar to the icachePort and dcachePort 
between CPU and memory, between different levels of caches in Ruby?




Thanks in advance


Fengze Yu 
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