The IRET instruction is implemented in arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py. It's fairly involved since IRET is an inherently complicated instruction, but it's commented and follows the pseudo code which was in the AMD manuals at the time it was written. Setting the trap flag in RFLAGS may not actually do anything in gem5 though, since this hasn't been a high priority for the sort of modelling people have wanted to do on it. There are mechanisms which will let you schedule an event on a CPU after it executes N more instructions, so at least in principle there should be most of what you'd need to implement it. There are some strange instructions which have an interrupt shadow which may not be interruptable with that flag, but I'd have to look at the documentation again to double check. The DelayedCommit mechanism was added a long time ago to help with those situations, where you may not be allowed to interrupt execution even between certain instructions, or even during others like the string instructions. I don't think that mechanism was fully fleshed out, but it's there if it helps.
Gabe On Tue, Oct 27, 2020 at 12:38 AM Deepak Mohan via gem5-users < [email protected]> wrote: > Hi, > Is single stepping supported in gem5 x86 (by setting the Trap Flag in > RFLAGS register) ? I was working with an educational OS that runs on gem5, > and was trying to add a single step feature to it. But when I set the Trap > flag in the RFLAGS saved on stack and called IRETQ instruction, it seems > that the Trap Flag is not set in the RFLAGS register. Can anyone provide > some information on this, like where to look in the gem5 source code to get > a better understanding. > > Thanks, > Deepak Mohan > _______________________________________________ > gem5-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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