On Fri, Nov 04, 2022 at 09:27:34AM +0100, Sebastian Huber wrote:
> Hello,
>
> even recent 32-bit architectures such as RISC-V do not support 64-bit atomic
> operations. Using -fprofile-update=atomic for the 32-bit RISC-V RV32GC ISA
> yields:
>
> warning: target does not support atomic profile update, single mode is
> selected
>
> For multi-threaded applications it is quite important to use atomic counter
> increments to get valid coverage data. I think this fall back is not really
> good. Maybe we should consider using this approach from Jakub Jelinek for
> 32-bit architectures lacking 64-bit atomic operations:
>
> if (__atomic_add_fetch_4 ((unsigned int *) &val, 1, __ATOMIC_RELAXED) ==
> 0)
> __atomic_fetch_add_4 (((unsigned int *) &val) + 1, 1, __ATOMIC_RELAXED);
>
> https://urldefense.com/v3/__https://patchwork.ozlabs.org/project/gcc/patch/[email protected]/*1447334__;Iw!!D9dNQwwGXtA!QgLVk_W5VF39jGPn64zfvbJ4IiAGApjLqzW7UkLWWuFD6ya4AAega4z4_tu2YquarSyTIl7qLzWvIefVpXkLKsAaeeIU63MtmQU$
>
> Last year I added the TARGET_GCOV_TYPE_SIZE target hook to optionally reduce
> the gcov type size to 32 bits. I am not really sure if this was a good idea.
> Longer running executables may observe counter overflows leading to invalid
> coverage data. If someone wants atomic updates, then the updates should be
> atomic even if this means to use a library implementation (libatomic).
>
> What about the following approach if -fprofile-update=atomic is given:
>
> 1. Use 64-bit atomics if available.
>
> 2. Use
>
> if (__atomic_add_fetch_4 ((unsigned int *) &val, 1, __ATOMIC_RELAXED) ==
> 0)
> __atomic_fetch_add_4 (((unsigned int *) &val) + 1, 1, __ATOMIC_RELAXED);
>
> if 32-bit atomics are available.
This assumes little-endian byte order.
Cheers,
Gabriel
>
> 3. Else use a library call (libatomic).
>
> --
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