On Sat, Jan 11, 2020 at 2:02 AM Andrew Pinski <pins...@gmail.com> wrote: > > Hi, > I was looking into reassoc (for PR 93131) and I noticed that the > alu.shift_reg is set to COSTS_N_INSNS (1). This prevents an > optimization where we combine some if statements into shifts. I > looked into the Corext A57 software optimization guide[1] and saw that > shift with a register has a latency of 1 which is the same as a shift > with an immediate. I looked in the history but it was there to begin > with. Is there a reason for this and would it be acceptable if we > change a57's costs to be correct? > > I looked into A65, A72, A75, A76, A77 and N1 software optimization > guides too and they have a similar thing of a latency of one cycle and > those are the ones which use the cortexa57_extra_costs variable too. > Note I could not find the A73 guide though.
I forgot to mention this causes lshift_cheap_p to return false which is not true for these cores. Thanks, Andrew Pinski > > Thanks, > Andrew Pinski > > > [1] > http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
