On Tue, Aug 20, 2019 at 9:07 AM John Darrington <j...@darrington.wattle.id.au> wrote: > > On Tue, Aug 20, 2019 at 08:56:39AM +0200, Richard Biener wrote: > > > Most of these suggestions involve adding some sort of virtual registers > > So I hacked the machine description to add two new registers Z1 and Z2 > > with the same mode as X and Y. > > > > Obviously the assembler balks at this. However the compiler still > > ICEs at the same place as before. > > > > So this suggests that our original diagnosis, viz: there are not enough > > address registers was not accurate, and in fact there is some other > > problem? > > That sounds likely. Given you have indirect addressing you could > simulate N virtual regs by placing them in a virtual reg table in memory > and accessed via a fixed address register (assuming all instructions > that would need an address reg also can take that indirect from memory). > > That was my plan. Accordingly, extending the md to provide N additional > regs (N currently = 2) was the first step. Having doubled the number > of available address registers, I had expected this would fix most of the > ICEs (but cause a lot of assembler errors). > > However it hasn't eliminated any ICEs. lra is still complaining > "unable to find a register to spill" So the plan seems to have fallen > over at the first hurdle. Why can it still not spill registers despite > having a lot more of them?
You really have to sit down and trace the LRA code with a debugger to tell... unfortunately the dumps aren't verbose enough to tell. Usually after spilling the insn constraints can still not be satisfied, the main question is usually why. Richard. > J'
