Hi!
On Sat, Aug 10, 2019 at 08:05:53AM +0200, John Darrington wrote:
> Choosing alt 5 in insn 14: (0) m (1) m {*movsi}
> 14: [r40:PSI+0x20]=[r41:PSI]
> Inserting insn reload before:
> 48: r40:PSI=r34:PSI
> 49: r41:PSI=[y:PSI+0x2f]
insn 14 is a mem-to-mem move (another feature not many more modern /
more RISCy CPUs have). That requires both of your address registers.
So far, so good. The reloads (insn 48 and 49) require address
registers themselves; that isn't necessarily a problem either. But
this requires careful juggling. Maybe you will need some backend code
for this, or to optimise this (although right now you just want it to
*work* :-) )
For some reason LRA didn't manage. Register inheritance seems to be
implicated (but that might be a red herring). Vladimir will probably
find out more, and/or correct me :-)
Segher
