On 01/06/18 10:23, Michael Clark wrote:
On 1/06/2018, at 6:16 PM, Sebastian Huber <sebastian.hu...@embedded-brains.de>
wrote:
On 29/05/18 20:02, Jim Wilson wrote:
Most variants include the C extension. Would it be possible to add -march=rv32g
and -march=rv64g variants?
The expectation is that most implementations will include the C extension. It
reduces code size, improves performance, and I think I read somewhere that it
takes only 400 gates to implement.
It isn't practical to try to support every possible combination of architecture
and ABI here, as there are too many possible combinations. But if there is a
major RISC-V target that is rv32g or rv64g then we should consider it. You can
of course define your own set of multilibs.
I am not a hardware developer, but I heard that the C extension is not easy to
implement in out of order machines.
Easy is relative.
The RISC-V ISA encoding has been designed so that wide fetch is relatively
easy, possibly an order of magnitude easier than an ISA with a complex variable
length encoding like x86.
RV64GC instruction lengths can be derived from the 2 least significant bits in
the first half-word packet of each instruction for mixed 16/32 bit
instructions. It does not require an attempt to parse multiple prefixes with
instructions ranging from 1 byte up to 15 bytes, before arriving at an
instruction length (x86). From that perspective RV64GC is decidedly simple.
That said, RV64GC is a little more complex than regular 32-bit encodings like
RV64G, PowerPC, AArch64, or SPARC.
I don’t think the paper you have linked to draws the conclusion you are
arriving at.
Yes, please use my words with care. I am not a hardware developer.
Reading "A.3 The Compressed (“C”) ISA Extension" in
https://github.com/ccelio/riscv-boom-doc/
lead me to this statement that it is not easy from my inexperienced
point of view.
--
Sebastian Huber, embedded brains GmbH
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