> On 02/09/2017 11:06 AM, Jakub Jelinek wrote: >> On Thu, Feb 09, 2017 at 01:47:33PM -0500, David Edelsohn wrote: >>> Freescale did not implement the POWER architecture. Again, POWER is a >>> comment about the original IBM POWER architecture (RIOS processors) >>> and used in RISC System/6000 computers, not the recent POWER >>> processors called POWER4, POWER5, POWER6, POWER7, POWER8, POWER9. >>> >>> lwsync is part of the ISA and Freescale did not fully implement the >>> architecture. >>> >>> Freescale or someone needs to implement a patch to target the >>> Freescale non-compliant processors. >> It seems with -mcpu=8540 and -mcpu=8548 you get sync instead of lwsync: >> /* E500 cores only support plain "sync", not lwsync. */ >> #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ >> || rs6000_cpu == PROCESSOR_PPC8548) >> The question is if all the CPUs you're using are these 2, or if you use some >> others that might not be superset of those. >> >> Jakub > > > We tried using e500, but on Freescale t1042 there was another instruction, > evstdd instruction which caused a fault. Andrii did the testing, he can > address > it better than I can.
evstdd is a Freescale SPE[1] instruction. The generation of SPE instructions can be disabled w/ -mno-spe (and maybe also supplemented with -mabi=no-spe). [1] http://www.nxp.com/assets/documents/data/en/reference-manuals/SPEPEM.pdf Arseny
