On 06/03/2015 12:53 AM, Richard Henderson wrote: > On 06/02/2015 08:32 AM, Andreas Krebbel wrote: >> -(define_insn "*<shift><mode>3" >> +(define_insn "*<shift><mode>3_reg" >> [(set (match_operand:GPR 0 "register_operand" "=d") >> (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") >> - (match_operand:SI 2 "shift_count_or_setmem_operand" >> "Y")))] >> + (match_operand:SI 2 "register_operand" "a")))] >> "" >> - "s<lr>l<g>\t%0,<1>%Y2" >> + "s<lr>l<g>\t%0,<1>%2" >> + [(set_attr "op_type" "RS<E>") >> + (set_attr "atype" "reg")]) >> + >> +(define_insn "*<shift><mode>3_imm" >> + [(set (match_operand:GPR 0 "register_operand" "=d") >> + (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") >> + (match_operand 2 "immediate_operand" "J")))] >> + "" >> + "s<lr>l<g>\t%0,<1>%2" >> + [(set_attr "op_type" "RS<E>") >> + (set_attr "atype" "reg")]) > > These two ought not be split apart. They're simple alternatives. Right. That was just a quick copy and paste hack to check if it works.
> And why SImode? Other modes would work as well since the instruction only uses the lower 6 bits anyway. But what's wrong with SImode? Bye, -Andreas-
