Hi David, I've worked on a gcc target that was porting an architecture without hardware interlock support. Basically, you need to emit nop operations to avoid possible hw conflicts. At the moment, this was done by patching the gcc scheduler to do so, Another issue to keep is to check for hardware conflicts across basic-block boundaries. And not the last, is to prohibit/avoid any instruction stream modification after scheduler (e.g., peephole optimizations etc.).
Best, Claudiu On Fri, Oct 31, 2014 at 8:03 PM, David Kang <dk...@isi.edu> wrote: > > Hello, > > I'm working on porting gcc to an architecture without hardware interlock > support for floating point unit. I read that instruction latency time can be > expressed in machine description file of gcc. I set the latency time of the > instructions and built gcc. > I expected that gcc would put the two dependent instructions apart > automatically > at least as many as the latency time of the first instruction. > However, my gcc doesn't do that. > I'm using a little old 4.7.3. > I also expected that gcc may fill the gap with no-op when it cannot find > other useful instructions to fill the gap. > But, I don't see that, either. > > Does gcc support an architecture without hardware interlock automatically? > Could anyone help me to understand how I can enforce the latency requirements > of two dependent instructions in gcc? > > I saw that GCC didn't support architectures without hardware interlocks in > the gcc mailing list > which is dated in 2007. (https://gcc.gnu.org/ml/gcc/2007-07/msg00915.html) > Is it still true? > > Thanks, > > David. > > -- > ---------------------- > Dr. Dong-In "David" Kang > Computer Scientist > USC/ISI
