On Thu, May 15, 2014 at 8:36 AM, Maxim Kuvyrkov <maxim.kuvyr...@linaro.org> wrote: > On May 15, 2014, at 6:46 PM, Ramana Radhakrishnan <ramana....@googlemail.com> > wrote: >> >>> >>> I'm not claiming it's a great heuristic or anything. There's bound to >>> be room for improvement. But it was based on "reality" and real results. >>> >>> Of course, if it turns out not be a win for ARM or s390x any more then it >>> should be disabled. >> >> The current situation that Kyrill is investigating is a case where we >> notice the first scheduler pass being a bit too aggressive with >> creating ILP opportunities with the A15 scheduler that causes >> performance differences with not turning on the first scheduler pass >> vs using the defaults. > > Charles has a work-in-progress patch that fixes a bug in SCHED_PRESSURE_MODEL > that causes the above symptoms. The bug causes 1st scheduler to > unnecessarily increase live ranges of pseudo registers when there are a lot > of instructions in the ready list.
Is this something that you've seen shows up in general integer code as well ? Do you or Charles have an example for us to look at ? I'm not sure what "lot of instructions in the ready list" really means here. The specific case Kyrill's been looking into is Dhrystone Proc_8 when tuned for a Cortex-A15 with neon and float-abi=hard but I am not sure if that has "too many instructions" :) . Kyrill, could you also look into the other cases we have from SPEC2k where we see this as well and come back with any specific testcases that Charles / Richard could also take a look into. > > Charles, can you finish your patch in the next several days and post it for > review? I think we'll await this but we'll go look into some of the benchmarks. Ramana > > Thank you, > > -- > Maxim Kuvyrkov > www.linaro.org > >
