On Fri, Apr 25, 2014 at 1:31 PM, Eric Botcazou <ebotca...@adacore.com> wrote: >> recent GCC versions support the C11 atomic operations for the SPARC LEON3 >> processor via the CASA instruction. GCC emits CASA instructions with an ASI >> of 0x80. I think this is due to the usage of "cas" if I get the stuff in >> sync.md right: >> >> "(define_insn "*atomic_compare_and_swap<mode>_1" >> [(set (match_operand:I48MODE 0 "register_operand" "=r") >> (match_operand:I48MODE 1 "mem_noofs_operand" "+w")) >> (set (match_dup 1) >> (unspec_volatile:I48MODE >> [(match_operand:I48MODE 2 "register_operand" "r") >> (match_operand:I48MODE 3 "register_operand" "0")] >> UNSPECV_CAS))] >> "(TARGET_V9 || TARGET_LEON3) && (<MODE>mode != DImode || TARGET_ARCH64)" >> "cas<modesuffix>\t%1, %2, %0" >> [(set_attr "type" "multi")])" > > Right, this is a bug, both in the compiler and the assembler, since an ASI of > 0x80 is not allowed for SPARC-V8. > >> According to the LEON3 manual we have: >> >> "6.2.7 Compare and Swap instruction (CASA) >> >> LEON4 implements the SPARC V9 Compare and Swap Alternative (CASA) >> instruction. The CASA operates as described in the SPARC V9 manual. The >> instruction is privileged, except when setting ASI = 0xA (user data)." >> >> I would like to use atomic operations in user mode. Is it possible to add a >> machine option to GCC to use an ASI of 0x0A for the atomic operations via >> CASA on LEON3? > > Yes, I guess we actually want to emit an ASI of either 0xA (user data) or 0xB > (supervisor data), predicated on -muser-mode. I'll prepare a patch.
Since we are using RTEMS on Leon3 (and maybe moving to Leon4), we're interested in getting this fixed too; feel free to assign us the issue to fix it if you have no time. Daniel. > > -- > Eric Botcazou -- Daniel F. Gutson Chief Engineering Officer, SPD San Lorenzo 47, 3rd Floor, Office 5 Córdoba, Argentina Phone: +54 351 4217888 / +54 351 4218211 Skype: dgutson
