Hi,
On Thu, 2013-02-28 at 11:10 +0000, Paulo Matos wrote:
> Hello,
>
> I am looking at how to correctly model in GCC predicate registers that
> have more than one bit and the value set into to the predicate register
> after a comparison depends on the size of the comparison.
>
> I have looked into GCC backends but haven't really found any backend
> with a similar constraint. Have I missed a backend that has similar
> requirements? If not, is there any way to currently (as of HEAD) model
> this in GCC?
Have you had a look at the SH backend? SH cores have a "T Bit"
register, which functions as carry bit, over/underflow, comparison
result and branch condition register. In the SH backend it's treated as
a fixed SImode hard-reg (although BImode would suffice in this case, I
guess).
Comparison patterns set the T bit, like:
(define_insn "cmpeqsi_t"
[(set (reg:SI T_REG)
(eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
(match_operand:SI 1 "arith_operand" "N,rI08,r")))]
Conditional branches use the T bit like:
(define_expand "branch_true"
[(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
(label_ref (match_operand 0))
(pc)))]
or:
(define_insn_and_split "*cbranch_t"
[(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
(label_ref (match_operand 0))
(pc)))]
where the predicate "cbranch_treg_value" looks like:
(define_predicate "cbranch_treg_value"
(match_code "eq,ne,reg,subreg,xor,sign_extend,zero_extend")
{
return sh_eval_treg_value (op) >= 0;
})
The predicate is for matching various forms of T bit negation patterns.
Maybe you could try the same approach for your case.
If your predicate register has multiple independent bit(fields), you
could try defining separate hard-regs for every bit(field).
Cheers,
Oleg
