On Sun, Sep 11, 2011 at 03:31:15PM -0400, Geert Bosch wrote:
> > On Sun, Sep 11, 2011 at 03:00:11PM -0400, Geert Bosch wrote:
> >> Also, for relaxed order atomic operations we would only need a single
> >> fence between two accesses (by a thread) to the same atomic object.
> >
> > I'm not aware of any CPUs that would need any kind of fences for that.
> > Nor the compiler should need any fences for that, MEMs that may (or even are
> > known to be aliased) aren't reordered.
>
> I guess for CPUs with TSO that might be right wrt. the hardware.
> I wouldn't say it is true in general.
You mean you are aware of CPUs that can reorder accesses to the same memory
location? If assembly has X = 5; Y = X; X = 6; where X is some memory
location that the operations don't happen in the program order?
> But all atomic operations on an atomic object M should have
> a total order. That means the compiler
>
> So for some atomic int X, with relaxed ordering:
>
> if (X == 0) X = 1;
> else X = 2;
>
> we can't optimize that to:
>
> X = 1;
> if (X != 0) X = 2;
Depends what actually you mean by X here, if it is some C++0x class
where X = value is __sync_mem_store, then even if it is a relaxed store,
nothing will try to optimize any of the stores or loads from it
(though, of course such a code is quite useless, because X may be changed
in between the test and the store).
Jakub
