Hi Vlad,
I found a problem with your IRA improvement checkin r171649 on 29-3-2011. I can't get picochip port to build with this change. The problem is in the function "clarify_prohibited_class_mode_regs" in ira.c:1413. The code reproduced here is

/* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
   spanning from one register pressure class to another one.  It is
   called after defining the pressure classes.  */
static void
clarify_prohibited_class_mode_regs (void)
{
  int j, k, hard_regno, cl, pclass, nregs;

  for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
    for (j = 0; j < NUM_MACHINE_MODES; j++)
      for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--)
        {
          hard_regno = ira_class_hard_regs[cl][k];
if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno))
            continue;
          nregs = hard_regno_nregs[hard_regno][j];
pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)];
          for (nregs-- ;nregs >= 0; nregs--)
            if (((enum reg_class) pclass
                 != ira_pressure_class_translate[REGNO_REG_CLASS
                                                 (hard_regno + nregs)]))
              {
                SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
                                  hard_regno);
                break;
              }
        }
}


I do not understand the functionality of the code, but i get a segfault in the line

            if (((enum reg_class) pclass
                 != ira_pressure_class_translate[REGNO_REG_CLASS
                                                 (hard_regno + nregs)]))

In the case where it segfaults, the hard_regno+nregs is greater than FIRST_PSEUDO_REGISTER. It leads to access beyond the end of REGNO_REG_CLASS array.

I realise that hard_regno_nregs happily gives you a value beyond the FIRST_PSEUDO_REGISTER. I can change it so it wouldn't do that, if that is the solution to this. Can you clarify?

Thanks
Hari

Reply via email to