Hello,
Can anyone familiar with backend explain to me when we use
VIRTUAL_STACK_VARS_REGNUM (or) VIRTUAL_STACK_DYNAMIC_REGNUM in gcc?
Rather, when does the compiler decide to allocate a variable to
stack_vars region and when to stack_dynamic?
I encountered some trouble with virtual-stack-vars. Since it gets
translated to FRAME_POINTER_REGNUM and we don't actually have a
dedicated frame pointer register in picochip, i got a compiler ICE. I
have set ELIMINABLE_REGS to eliminate FRAME_POINTER in preference to
STACK_POINTER, but it doesn't work in this case (presumably
because FRAME_POINTER is used in a memory reference and elimination does
not work well with memory)
In the attached C code, at expand it saves the result from each call to
getPort function to the virtual_stack_vars region and then copies it
from there into virtual_stack_dynamic region. Why can it not copy
straight into virtual_stack_dynamic region? In the example, if i were to
write to the "int32_elements" instead of cmplx_elements, it does work
fine by writing it directly into virtual_stack_dynamic region.
I have attached the compiler dumps from expand, sched and ira for reference.
I tried this on GCC 4.6.0 release compiler. The port has had some local
changes for vector support, which i will submit into mainline after a while.
Cheers
Hari
#include<stdint.h>
#define vector __attribute__((vector_size(16) ))
typedef signed short integer16;
typedef signed long integer32;
typedef struct complex16 {
integer16 re;
integer16 im;
} complex16;
long __builtin_get (int);
static inline complex16 getPort1(void) __attribute__((always_inline));
static inline complex16 getPort1(void) {
union{complex16 actualValue; long rawValue; } converter;
converter.rawValue = __builtin_get(1);
return converter.actualValue;
}
typedef union
{
complex16 cmplx_elements[4];
int32_t int32_elements[4];
vector int all_elements;
} vectComplex;
int fn1 (vector int * a)
{
vectComplex x;
x.cmplx_elements [0] = getPort1();
x.cmplx_elements [1] = getPort1();
x.cmplx_elements [2] = getPort1();
x.cmplx_elements [3] = getPort1();
a[0] = x.all_elements;
return 5;
}
;; Function fn1 (fn1)
fn1 (vector(8) int * a)
{
long int D.2134;
struct complex16 D.2133;
long int D.2129;
struct complex16 D.2128;
long int D.2124;
struct complex16 D.2123;
long int D.2119;
struct complex16 D.2118;
union vectComplex x;
vector(8) int D.2106;
# BLOCK 2 freq:10000
# PRED: ENTRY [100.0%] (fallthru,exec)
D.2119_10 = __builtin_get (1);
# DEBUG converter$rawValue => D.2119_10
MEM[(struct complex16 *)&D.2118].rawValue = D.2119_10;
x.cmplx_elements[0] = D.2118;
D.2124_11 = __builtin_get (1);
# DEBUG converter$rawValue => D.2124_11
MEM[(struct complex16 *)&D.2123].rawValue = D.2124_11;
x.cmplx_elements[1] = D.2123;
D.2129_12 = __builtin_get (1);
# DEBUG converter$rawValue => D.2129_12
MEM[(struct complex16 *)&D.2128].rawValue = D.2129_12;
x.cmplx_elements[2] = D.2128;
D.2134_13 = __builtin_get (1);
# DEBUG converter$rawValue => D.2134_13
MEM[(struct complex16 *)&D.2133].rawValue = D.2134_13;
x.cmplx_elements[3] = D.2133;
D.2106_1 = x.all_elements;
*a_2(D) = D.2106_1;
return 5;
# SUCC: EXIT [100.0%]
}
Partition map
Partition 1 (D.2106_1 - 1 )
Partition 2 (a_2(D) - 2 )
Partition 4 (.MEM_4(D) - 4 )
Partition 5 (.MEM_5 - 5 )
Partition 6 (.MEM_6 - 6 )
Partition 7 (.MEM_7 - 7 )
Partition 8 (.MEM_8 - 8 )
Partition 9 (.MEM_9 - 9 )
Partition 10 (D.2119_10 - 10 )
Partition 11 (D.2124_11 - 11 )
Partition 12 (D.2129_12 - 12 )
Partition 13 (D.2134_13 - 13 )
Partition 14 (.MEM_14 - 14 )
Partition 15 (.MEM_15 - 15 )
Partition 16 (.MEM_16 - 16 )
Partition 17 (.MEM_17 - 17 )
Partition 18 (.MEM_18 - 18 )
Partition 19 (.MEM_19 - 19 )
Partition 20 (.MEM_20 - 20 )
Partition 21 (.MEM_21 - 21 )
Partition 22 (.MEM_22 - 22 )
Partition 23 (.MEM_23 - 23 )
Partition 24 (.MEM_24 - 24 )
Partition 25 (.MEM_25 - 25 )
Partition map
Partition 0 (a_2(D) - 2 )
Live on entry to BB2 : a_2(D)
Conflict graph:
After sorting:
Coalesce List:
Partition map
Partition 0 (a_2(D) - 2 )
After Coalescing:
Partition map
Partition 0 (D.2106_1 - 1 )
Partition 1 (a_2(D) - 2 )
Partition 2 (D.2119_10 - 10 )
Partition 3 (D.2124_11 - 11 )
Partition 4 (D.2129_12 - 12 )
Partition 5 (D.2134_13 - 13 )
Replacing Expressions
D.2106_1 replace with --> D.2106_1 = x.all_elements;
fn1 (vector(8) int * a)
{
long int D.2134;
struct complex16 D.2133;
long int D.2129;
struct complex16 D.2128;
long int D.2124;
struct complex16 D.2123;
long int D.2119;
struct complex16 D.2118;
union vectComplex x;
vector(8) int D.2106;
# BLOCK 2 freq:10000
# PRED: ENTRY [100.0%] (fallthru,exec)
D.2119_10 = __builtin_get (1);
# DEBUG converter$rawValue => D.2119_10
MEM[(struct complex16 *)&D.2118].rawValue = D.2119_10;
x.cmplx_elements[0] = D.2118;
D.2124_11 = __builtin_get (1);
# DEBUG converter$rawValue => D.2124_11
MEM[(struct complex16 *)&D.2123].rawValue = D.2124_11;
x.cmplx_elements[1] = D.2123;
D.2129_12 = __builtin_get (1);
# DEBUG converter$rawValue => D.2129_12
MEM[(struct complex16 *)&D.2128].rawValue = D.2129_12;
x.cmplx_elements[2] = D.2128;
D.2134_13 = __builtin_get (1);
# DEBUG converter$rawValue => D.2134_13
MEM[(struct complex16 *)&D.2133].rawValue = D.2134_13;
x.cmplx_elements[3] = D.2133;
D.2106_1 = x.all_elements;
*a_2(D) = D.2106_1;
return 5;
# SUCC: EXIT [100.0%]
}
Partition 4: size 16 align 16
x, offset 0
Partition 0: size 4 align 2
D.2133, offset 0
Partition 1: size 4 align 2
D.2128, offset 0
Partition 2: size 4 align 2
D.2123, offset 0
Partition 3: size 4 align 2
D.2118, offset 0
;; Generating RTL for gimple basic block 2
;; D.2119_10 = __builtin_get (1);
(insn 11 10 0 (set (reg:SI 43 [ D.2119 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 -1
(nil))
;; # DEBUG converter$rawValue => D.2119_10
(debug_insn 12 11 0 (var_location:SI converter$rawValue (const_int 0 [0]))
test.c:17 -1
(nil))
;; MEM[(struct complex16 *)&D.2118].rawValue = D.2119_10;
(insn 13 12 14 (parallel [
(set (reg/f:HI 53)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 12 [0xc])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 14 13 0 (set (mem/s/c:SI (reg/f:HI 53) [0 MEM[(struct complex16
*)&D.2118].rawValue+0 S4 A32])
(reg:SI 43 [ D.2119 ])) test.c:18 -1
(nil))
;; x.cmplx_elements[0] = D.2118;
(insn 15 14 16 (parallel [
(set (reg/f:HI 54)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 12 [0xc])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 16 15 0 (set (mem/s/c:SI (reg/f:HI 50) [0 x.cmplx_elements+0 S4 A128])
(mem/s/c:SI (reg/f:HI 54) [3 D.2118+0 S4 A32])) test.c:18 -1
(nil))
;; D.2124_11 = __builtin_get (1);
(insn 17 16 0 (set (reg:SI 44 [ D.2124 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 -1
(nil))
;; # DEBUG converter$rawValue => D.2124_11
(debug_insn 18 17 0 (var_location:SI converter$rawValue (const_int 0 [0]))
test.c:17 -1
(nil))
;; MEM[(struct complex16 *)&D.2123].rawValue = D.2124_11;
(insn 19 18 20 (parallel [
(set (reg/f:HI 55)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 8 [0x8])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 20 19 0 (set (mem/s/c:SI (reg/f:HI 55) [0 MEM[(struct complex16
*)&D.2123].rawValue+0 S4 A32])
(reg:SI 44 [ D.2124 ])) test.c:18 -1
(nil))
;; x.cmplx_elements[1] = D.2123;
(insn 21 20 22 (parallel [
(set (reg/f:HI 56)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 8 [0x8])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 22 21 0 (set (mem/s/c:SI (plus:HI (reg/f:HI 50)
(const_int 4 [0x4])) [0 x.cmplx_elements+4 S4 A32])
(mem/s/c:SI (reg/f:HI 56) [3 D.2123+0 S4 A32])) test.c:18 -1
(nil))
;; D.2129_12 = __builtin_get (1);
(insn 23 22 0 (set (reg:SI 45 [ D.2129 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 -1
(nil))
;; # DEBUG converter$rawValue => D.2129_12
(debug_insn 24 23 0 (var_location:SI converter$rawValue (const_int 0 [0]))
test.c:17 -1
(nil))
;; MEM[(struct complex16 *)&D.2128].rawValue = D.2129_12;
(insn 25 24 26 (parallel [
(set (reg/f:HI 57)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 4 [0x4])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 26 25 0 (set (mem/s/c:SI (reg/f:HI 57) [0 MEM[(struct complex16
*)&D.2128].rawValue+0 S4 A32])
(reg:SI 45 [ D.2129 ])) test.c:18 -1
(nil))
;; x.cmplx_elements[2] = D.2128;
(insn 27 26 28 (parallel [
(set (reg/f:HI 58)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 4 [0x4])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 28 27 0 (set (mem/s/c:SI (plus:HI (reg/f:HI 50)
(const_int 8 [0x8])) [0 x.cmplx_elements+8 S4 A64])
(mem/s/c:SI (reg/f:HI 58) [3 D.2128+0 S4 A32])) test.c:18 -1
(nil))
;; D.2134_13 = __builtin_get (1);
(insn 29 28 0 (set (reg:SI 46 [ D.2134 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 -1
(nil))
;; # DEBUG converter$rawValue => D.2134_13
(debug_insn 30 29 0 (var_location:SI converter$rawValue (const_int 0 [0]))
test.c:17 -1
(nil))
;; MEM[(struct complex16 *)&D.2133].rawValue = D.2134_13;
(insn 31 30 32 (set (reg/f:HI 59)
(reg/f:HI 37 virtual-stack-vars)) test.c:18 -1
(nil))
(insn 32 31 0 (set (mem/s/c:SI (reg/f:HI 59) [0 MEM[(struct complex16
*)&D.2133].rawValue+0 S4 A32])
(reg:SI 46 [ D.2134 ])) test.c:18 -1
(nil))
;; x.cmplx_elements[3] = D.2133;
(insn 33 32 34 (set (reg/f:HI 60)
(reg/f:HI 37 virtual-stack-vars)) test.c:18 -1
(nil))
(insn 34 33 0 (set (mem/s/c:SI (plus:HI (reg/f:HI 50)
(const_int 12 [0xc])) [0 x.cmplx_elements+12 S4 A32])
(mem/s/c:SI (reg/f:HI 60) [3 D.2133+0 S4 A32])) test.c:18 -1
(nil))
;; *a_2(D) = D.2106_1;
(insn 35 34 0 (set (mem:V8HI (reg/v/f:HI 52 [ a ]) [6 *a_2(D)+0 S16 A128])
(mem/s/c:V8HI (reg/f:HI 50) [0 x.all_elements+0 S16 A128])) test.c:35 -1
(nil))
;; return 5;
(insn 36 35 37 (set (reg:HI 51 [ <retval> ])
(const_int 5 [0x5])) test.c:36 -1
(nil))
(jump_insn 37 36 38 (set (pc)
(label_ref 0)) test.c:36 -1
(nil))
(barrier 38 37 0)
;;
;; Full RTL generated for this function:
;;
(note 1 0 9 NOTE_INSN_DELETED)
;; Start of basic block ( 0) -> 2
;; Pred edge ENTRY [100.0%] (fallthru)
(note 9 1 7 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 7 9 43 2 (set (reg/v/f:HI 52 [ a ])
(reg:HI 0 R0 [ a ])) test.c:29 -1
(nil))
(insn 43 7 2 2 (set (reg:HI 62)
(reg/f:HI 13 FP)) test.c:37 -1
(nil))
(insn 2 43 3 2 (parallel [
(set (reg/f:HI 13 FP)
(plus:HI (reg/f:HI 13 FP)
(const_int -32 [0xffffffffffffffe0])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:29 -1
(nil))
(insn 3 2 4 2 (set (reg:HI 47)
(reg/f:HI 38 virtual-stack-dynamic)) test.c:29 -1
(nil))
(insn 4 3 5 2 (parallel [
(set (reg:HI 48)
(plus:HI (reg:HI 47)
(const_int 15 [0xf])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:29 -1
(nil))
(insn 5 4 6 2 (set (reg:HI 49)
(lshiftrt:HI (reg:HI 48)
(const_int 4 [0x4]))) test.c:29 -1
(expr_list:REG_EQUAL (udiv:HI (reg:HI 48)
(const_int 16 [0x10]))
(nil)))
(insn 6 5 8 2 (set (reg/f:HI 50)
(ashift:HI (reg:HI 49)
(const_int 4 [0x4]))) test.c:29 -1
(nil))
(note 8 6 10 2 NOTE_INSN_FUNCTION_BEG)
;; End of basic block 2 -> ( 3)
;; Succ edge 3 [100.0%] (fallthru)
;; Start of basic block ( 2) -> 3
;; Pred edge 2 [100.0%] (fallthru)
(note 10 8 11 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 11 10 12 3 (set (reg:SI 43 [ D.2119 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 -1
(nil))
(debug_insn 12 11 13 3 (var_location:SI converter$rawValue (reg:SI 43 [ D.2119
])) test.c:17 -1
(nil))
(insn 13 12 14 3 (parallel [
(set (reg/f:HI 53)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 12 [0xc])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 14 13 15 3 (set (mem/s/c:SI (reg/f:HI 53) [0 MEM[(struct complex16
*)&D.2118].rawValue+0 S4 A32])
(reg:SI 43 [ D.2119 ])) test.c:18 -1
(nil))
(insn 15 14 16 3 (parallel [
(set (reg/f:HI 54)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 12 [0xc])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 16 15 17 3 (set (mem/s/c:SI (reg/f:HI 50) [0 x.cmplx_elements+0 S4 A128])
(mem/s/c:SI (reg/f:HI 54) [3 D.2118+0 S4 A32])) test.c:18 -1
(nil))
(insn 17 16 18 3 (set (reg:SI 44 [ D.2124 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 -1
(nil))
(debug_insn 18 17 19 3 (var_location:SI converter$rawValue (reg:SI 44 [ D.2124
])) test.c:17 -1
(nil))
(insn 19 18 20 3 (parallel [
(set (reg/f:HI 55)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 8 [0x8])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 20 19 21 3 (set (mem/s/c:SI (reg/f:HI 55) [0 MEM[(struct complex16
*)&D.2123].rawValue+0 S4 A32])
(reg:SI 44 [ D.2124 ])) test.c:18 -1
(nil))
(insn 21 20 22 3 (parallel [
(set (reg/f:HI 56)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 8 [0x8])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 22 21 23 3 (set (mem/s/c:SI (plus:HI (reg/f:HI 50)
(const_int 4 [0x4])) [0 x.cmplx_elements+4 S4 A32])
(mem/s/c:SI (reg/f:HI 56) [3 D.2123+0 S4 A32])) test.c:18 -1
(nil))
(insn 23 22 24 3 (set (reg:SI 45 [ D.2129 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 -1
(nil))
(debug_insn 24 23 25 3 (var_location:SI converter$rawValue (reg:SI 45 [ D.2129
])) test.c:17 -1
(nil))
(insn 25 24 26 3 (parallel [
(set (reg/f:HI 57)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 4 [0x4])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 26 25 27 3 (set (mem/s/c:SI (reg/f:HI 57) [0 MEM[(struct complex16
*)&D.2128].rawValue+0 S4 A32])
(reg:SI 45 [ D.2129 ])) test.c:18 -1
(nil))
(insn 27 26 28 3 (parallel [
(set (reg/f:HI 58)
(plus:HI (reg/f:HI 37 virtual-stack-vars)
(const_int 4 [0x4])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 -1
(nil))
(insn 28 27 29 3 (set (mem/s/c:SI (plus:HI (reg/f:HI 50)
(const_int 8 [0x8])) [0 x.cmplx_elements+8 S4 A64])
(mem/s/c:SI (reg/f:HI 58) [3 D.2128+0 S4 A32])) test.c:18 -1
(nil))
(insn 29 28 30 3 (set (reg:SI 46 [ D.2134 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 -1
(nil))
(debug_insn 30 29 31 3 (var_location:SI converter$rawValue (reg:SI 46 [ D.2134
])) test.c:17 -1
(nil))
(insn 31 30 32 3 (set (reg/f:HI 59)
(reg/f:HI 37 virtual-stack-vars)) test.c:18 -1
(nil))
(insn 32 31 33 3 (set (mem/s/c:SI (reg/f:HI 59) [0 MEM[(struct complex16
*)&D.2133].rawValue+0 S4 A32])
(reg:SI 46 [ D.2134 ])) test.c:18 -1
(nil))
(insn 33 32 34 3 (set (reg/f:HI 60)
(reg/f:HI 37 virtual-stack-vars)) test.c:18 -1
(nil))
(insn 34 33 35 3 (set (mem/s/c:SI (plus:HI (reg/f:HI 50)
(const_int 12 [0xc])) [0 x.cmplx_elements+12 S4 A32])
(mem/s/c:SI (reg/f:HI 60) [3 D.2133+0 S4 A32])) test.c:18 -1
(nil))
(insn 35 34 36 3 (set (mem:V8HI (reg/v/f:HI 52 [ a ]) [6 *a_2(D)+0 S16 A128])
(mem/s/c:V8HI (reg/f:HI 50) [0 x.all_elements+0 S16 A128])) test.c:35 -1
(nil))
(insn 36 35 37 3 (set (reg:HI 51 [ <retval> ])
(const_int 5 [0x5])) test.c:36 -1
(nil))
(jump_insn 37 36 38 3 (set (pc)
(label_ref 39)) test.c:36 -1
(nil)
-> 39)
;; End of basic block 3 -> ( 5)
;; Succ edge 5 [100.0%]
(barrier 38 37 48)
;; Start of basic block () -> 4
(note 48 38 41 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 41 48 42 4 (clobber (reg/i:HI 0 R0)) test.c:37 -1
(nil))
(insn 42 41 39 4 (clobber (reg:HI 51 [ <retval> ])) test.c:37 -1
(nil))
;; End of basic block 4 -> ( 5)
;; Succ edge 5 [100.0%] (fallthru)
;; Start of basic block ( 3 4) -> 5
;; Pred edge 3 [100.0%]
;; Pred edge 4 [100.0%] (fallthru)
(code_label 39 42 49 5 1 "" [1 uses])
(note 49 39 40 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 40 49 44 5 (set (reg/i:HI 0 R0)
(reg:HI 51 [ <retval> ])) test.c:37 -1
(nil))
(insn 44 40 45 5 (clobber (mem:BLK (scratch) [0 A8])) test.c:37 -1
(nil))
(insn 45 44 46 5 (clobber (mem:BLK (reg/f:HI 13 FP) [0 A8])) test.c:37 -1
(nil))
(insn 46 45 47 5 (set (reg/f:HI 13 FP)
(reg:HI 62)) test.c:37 -1
(nil))
(insn 47 46 0 5 (use (reg/i:HI 0 R0)) test.c:37 -1
(nil))
;; End of basic block 5 -> ( 1)
;; Succ edge EXIT [100.0%] (fallthru)
;; Function fn1 (fn1)
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
deleting insn with uid = 5.
deleting insn with uid = 8.
deleting insn with uid = 36.
;; ======================================================
;; -- basic block 2 from 7 to 47 -- before reload
;; ======================================================
;; Clock 0
;; 0--> 43 r62=FP :slot0|slot1
;; 0--> 2 {FP=FP-0x20;clobber pseudoCC;}
:(slot0+slot1)|(slot1+slot2)|(slot0+slot2)
;; Clock 1
;; 1--> 7 r52=R0 :slot0|slot1
;; Clock 2
;; 2--> 4 {r48=FP+0xf;clobber pseudoCC;} :slot0|slot1
;; Clock 4
;; 4--> 6
{r50=r48&0xfffffffffffffff0;clobbe:(slot0+slot1)|(slot1+slot2)|(slot0+slot2)
;; Clock 6
;; 6--> 11 r43=unspec/v[0x1] 8 :slot1
;; 6--> 12: debug converter$rawValue => r43 :nothing
;; Clock 7
;; 7--> 13 {r53=pseudoFP+0xc;clobber pseudoCC:slot0|slot1
;; 7--> 16 [r50]=r43 :slot1,nothing
;; Clock 9
;; 9--> 14 [r53]=r43 :slot1,nothing
;; Clock 10
;; 10--> 17 r44=unspec/v[0x1] 8 :slot1
;; 10--> 18: debug converter$rawValue => r44 :nothing
;; Clock 11
;; 11--> 19 {r55=pseudoFP+0x8;clobber pseudoCC:slot0|slot1
;; 11--> 22 [r50+0x4]=r44 :slot1,nothing
;; Clock 13
;; 13--> 20 [r55]=r44 :slot1,nothing
;; Clock 14
;; 14--> 23 r45=unspec/v[0x1] 8 :slot1
;; 14--> 24: debug converter$rawValue => r45 :nothing
;; Clock 15
;; 15--> 25 {r57=pseudoFP+0x4;clobber pseudoCC:slot0|slot1
;; 15--> 28 [r50+0x8]=r45 :slot1,nothing
;; Clock 17
;; 17--> 26 [r57]=r45 :slot1,nothing
;; Clock 18
;; 18--> 29 r46=unspec/v[0x1] 8 :slot1
;; 18--> 30: debug converter$rawValue => r46 :nothing
;; Clock 19
;; 19--> 34 [r50+0xc]=r46 :slot1,nothing
;; 19--> 31 r59=pseudoFP :slot0|slot1
;; Clock 20
;; 20--> 40 R0=0x5 :slot0|slot1
;; 20--> 32 [r59]=r46 :slot1,nothing
;; Clock 25
;; 25--> 35 [r52]=[r50] :slot2
;; 25--> 44 clobber [scratch] :nothing
;; 25--> 45 clobber [FP] :nothing
;; 25--> 46 FP=r62 :slot0|slot1
;; 25--> 47 use R0 :nothing
;; Ready list (final):
;; total time = 25
;; new head = 7
;; new tail = 47
;; Procedure interblock/speculative motions == 0/0
fn1
Dataflow summary:
;; invalidated by call 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 12
[R12] 17 [pseudoCC] 20 [V0] 21 [V1] 22 [V2] 23 [V3] 24 [V4] 25 [V5] 26 [V6] 27
[V7] 28 [V8] 29 [V9] 30 [V10] 31 [V11] 32 [V12] 33 [V13] 34 [V14] 35 [V15]
;; hardware regs used 13 [FP] 18 [pseudoFP] 19 [pseudoAP]
;; regular block artificial uses 13 [FP] 18 [pseudoFP] 19 [pseudoAP]
;; eh block artificial uses 13 [FP] 18 [pseudoFP] 19 [pseudoAP]
;; entry block defs 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 12 [R12] 13
[FP] 18 [pseudoFP] 19 [pseudoAP]
;; exit block uses 0 [R0] 13 [FP] 18 [pseudoFP]
;; regs ever live 0[R0] 13[FP] 17[pseudoCC]
;; ref usage r0={2d,3u} r1={1d} r2={1d} r3={1d} r4={1d} r5={1d} r12={1d}
r13={3d,8u} r17={6d} r18={1d,6u} r19={1d,1u} r43={1d,3u} r44={1d,3u}
r45={1d,3u} r46={1d,3u} r48={1d,1u} r50={1d,5u} r52={1d,1u} r53={1d,1u}
r55={1d,1u} r57={1d,1u} r59={1d,1u} r62={1d,1u}
;; total ref usage 73{31d,42u,0e} in 31{31 regular + 0 call} insns.
(note 1 0 9 NOTE_INSN_DELETED)
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(13){ }u1(18){ }u2(19){ }}
;; lr in 0 [R0] 13 [FP] 18 [pseudoFP] 19 [pseudoAP]
;; lr use 0 [R0] 13 [FP] 18 [pseudoFP] 19 [pseudoAP]
;; lr def 0 [R0] 13 [FP] 17 [pseudoCC] 43 44 45 46 48 50 52 53 55 57 59
62
;; live in 0 [R0] 13 [FP] 18 [pseudoFP] 19 [pseudoAP]
;; live gen 0 [R0] 13 [FP] 43 44 45 46 48 50 52 53 55 57 59 62
;; live kill 17 [pseudoCC]
;; Pred edge ENTRY [100.0%] (fallthru)
(note 9 1 5 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 5 9 8 2 NOTE_INSN_DELETED)
(note 8 5 36 2 NOTE_INSN_FUNCTION_BEG)
(note 36 8 43 2 NOTE_INSN_DELETED)
(insn 43 36 2 2 (set (reg/f:HI 62)
(reg/f:HI 13 FP)) test.c:37 15 {movhi}
(nil))
(insn 2 43 7 2 (parallel [
(set (reg/f:HI 13 FP)
(plus:HI (reg/f:HI 13 FP)
(const_int -32 [0xffffffffffffffe0])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:29 24 {addhi3}
(expr_list:REG_UNUSED (reg:CC 17 pseudoCC)
(nil)))
(insn 7 2 4 2 (set (reg/v/f:HI 52 [ a ])
(reg:HI 0 R0 [ a ])) test.c:29 15 {movhi}
(expr_list:REG_DEAD (reg:HI 0 R0 [ a ])
(nil)))
(insn 4 7 6 2 (parallel [
(set (reg/f:HI 48)
(plus:HI (reg/f:HI 13 FP)
(const_int 15 [0xf])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:29 24 {addhi3}
(expr_list:REG_UNUSED (reg:CC 17 pseudoCC)
(nil)))
(insn 6 4 11 2 (parallel [
(set (reg/f:HI 50)
(and:HI (reg/f:HI 48)
(const_int -16 [0xfffffffffffffff0])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:29 58 {andhi3}
(expr_list:REG_DEAD (reg/f:HI 48)
(expr_list:REG_UNUSED (reg:CC 17 pseudoCC)
(nil))))
(insn 11 6 12 2 (set (reg:SI 43 [ D.2119 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 81 {commsGet}
(nil))
(debug_insn 12 11 13 2 (var_location:SI converter$rawValue (reg:SI 43 [ D.2119
])) test.c:17 -1
(nil))
(insn 13 12 16 2 (parallel [
(set (reg/f:HI 53)
(plus:HI (reg/f:HI 18 pseudoFP)
(const_int 12 [0xc])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 24 {addhi3}
(expr_list:REG_UNUSED (reg:CC 17 pseudoCC)
(nil)))
(insn 16 13 14 2 (set (mem/s/c:SI (reg/f:HI 50) [0 x.cmplx_elements+0 S4 A128])
(reg:SI 43 [ D.2119 ])) test.c:18 16 {movsi}
(expr_list:REG_DEAD (reg:SI 43 [ D.2119 ])
(nil)))
(insn 14 16 17 2 (set (mem/s/c:SI (reg/f:HI 53) [0 MEM[(struct complex16
*)&D.2118].rawValue+0 S4 A32])
(reg:SI 43 [ D.2119 ])) test.c:18 16 {movsi}
(expr_list:REG_DEAD (reg/f:HI 53)
(nil)))
(insn 17 14 18 2 (set (reg:SI 44 [ D.2124 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 81 {commsGet}
(nil))
(debug_insn 18 17 19 2 (var_location:SI converter$rawValue (reg:SI 44 [ D.2124
])) test.c:17 -1
(nil))
(insn 19 18 22 2 (parallel [
(set (reg/f:HI 55)
(plus:HI (reg/f:HI 18 pseudoFP)
(const_int 8 [0x8])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 24 {addhi3}
(expr_list:REG_UNUSED (reg:CC 17 pseudoCC)
(nil)))
(insn 22 19 20 2 (set (mem/s/c:SI (plus:HI (reg/f:HI 50)
(const_int 4 [0x4])) [0 x.cmplx_elements+4 S4 A32])
(reg:SI 44 [ D.2124 ])) test.c:18 16 {movsi}
(expr_list:REG_DEAD (reg:SI 44 [ D.2124 ])
(nil)))
(insn 20 22 23 2 (set (mem/s/c:SI (reg/f:HI 55) [0 MEM[(struct complex16
*)&D.2123].rawValue+0 S4 A32])
(reg:SI 44 [ D.2124 ])) test.c:18 16 {movsi}
(expr_list:REG_DEAD (reg/f:HI 55)
(nil)))
(insn 23 20 24 2 (set (reg:SI 45 [ D.2129 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 81 {commsGet}
(nil))
(debug_insn 24 23 25 2 (var_location:SI converter$rawValue (reg:SI 45 [ D.2129
])) test.c:17 -1
(nil))
(insn 25 24 28 2 (parallel [
(set (reg/f:HI 57)
(plus:HI (reg/f:HI 18 pseudoFP)
(const_int 4 [0x4])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:18 24 {addhi3}
(expr_list:REG_UNUSED (reg:CC 17 pseudoCC)
(nil)))
(insn 28 25 26 2 (set (mem/s/c:SI (plus:HI (reg/f:HI 50)
(const_int 8 [0x8])) [0 x.cmplx_elements+8 S4 A64])
(reg:SI 45 [ D.2129 ])) test.c:18 16 {movsi}
(expr_list:REG_DEAD (reg:SI 45 [ D.2129 ])
(nil)))
(insn 26 28 29 2 (set (mem/s/c:SI (reg/f:HI 57) [0 MEM[(struct complex16
*)&D.2128].rawValue+0 S4 A32])
(reg:SI 45 [ D.2129 ])) test.c:18 16 {movsi}
(expr_list:REG_DEAD (reg/f:HI 57)
(nil)))
(insn 29 26 30 2 (set (reg:SI 46 [ D.2134 ])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 81 {commsGet}
(nil))
(debug_insn 30 29 34 2 (var_location:SI converter$rawValue (reg:SI 46 [ D.2134
])) test.c:17 -1
(nil))
(insn 34 30 31 2 (set (mem/s/c:SI (plus:HI (reg/f:HI 50)
(const_int 12 [0xc])) [0 x.cmplx_elements+12 S4 A32])
(reg:SI 46 [ D.2134 ])) test.c:18 16 {movsi}
(expr_list:REG_DEAD (reg:SI 46 [ D.2134 ])
(nil)))
(insn 31 34 40 2 (set (reg/f:HI 59)
(reg/f:HI 18 pseudoFP)) test.c:18 15 {movhi}
(nil))
(insn 40 31 32 2 (set (reg/i:HI 0 R0)
(const_int 5 [0x5])) test.c:37 15 {movhi}
(expr_list:REG_EQUAL (const_int 5 [0x5])
(nil)))
(insn 32 40 35 2 (set (mem/s/c:SI (reg/f:HI 59) [0 MEM[(struct complex16
*)&D.2133].rawValue+0 S4 A32])
(reg:SI 46 [ D.2134 ])) test.c:18 16 {movsi}
(expr_list:REG_DEAD (reg/f:HI 59)
(nil)))
(insn 35 32 44 2 (set (mem:V8HI (reg/v/f:HI 52 [ a ]) [6 *a_2(D)+0 S16 A128])
(mem/s/c:V8HI (reg/f:HI 50) [0 x.all_elements+0 S16 A128])) test.c:35
92 {movv8hi_loadstore}
(expr_list:REG_DEAD (reg/v/f:HI 52 [ a ])
(expr_list:REG_DEAD (reg/f:HI 50)
(nil))))
(insn 44 35 45 2 (clobber (mem:BLK (scratch) [0 A8])) test.c:37 -1
(nil))
(insn 45 44 46 2 (clobber (mem:BLK (reg/f:HI 13 FP) [0 A8])) test.c:37 -1
(nil))
(insn 46 45 47 2 (set (reg/f:HI 13 FP)
(reg/f:HI 62)) test.c:37 15 {movhi}
(expr_list:REG_DEAD (reg/f:HI 62)
(nil)))
(insn 47 46 50 2 (use (reg/i:HI 0 R0)) test.c:37 -1
(nil))
;; End of basic block 2 -> ( 1)
;; lr out 0 [R0] 13 [FP] 18 [pseudoFP] 19 [pseudoAP]
;; live out 0 [R0] 13 [FP] 18 [pseudoFP] 19 [pseudoAP]
;; Succ edge EXIT [100.0%] (fallthru)
(note 50 47 0 NOTE_INSN_DELETED)
starting the processing of deferred insns
ending the processing of deferred insns
;; Function fn1 (fn1)
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
scanning new insn with uid = 51.
rescanning insn with uid = 51.
deleting insn with uid = 51.
deleting insn with uid = 31.
Building IRA IR
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue:n_basic_blocks 3 n_edges 2 count 3 ( 1)
df_worklist_dataflow_doublequeue:n_basic_blocks 3 n_edges 2 count 3 ( 1)
init_insns for 53: (insn_list:REG_DEP_TRUE 13 (nil))
init_insns for 55: (insn_list:REG_DEP_TRUE 19 (nil))
init_insns for 57: (insn_list:REG_DEP_TRUE 25 (nil))
init_insns for 59: (insn_list:REG_DEP_TRUE 51 (nil))
Reg 53 has equivalence, initial gains 8000
Reg 55 has equivalence, initial gains 8000
Reg 57 has equivalence, initial gains 8000
Reg 59 has equivalence, initial gains 8000
Pass 0 for finding pseudo/allocno costs
a0 (r62,l0) best GR_REGS, cover GR_REGS
a3 (r59,l0) best NO_REGS, cover NO_REGS
a5 (r57,l0) best NO_REGS, cover NO_REGS
a7 (r55,l0) best NO_REGS, cover NO_REGS
a9 (r53,l0) best NO_REGS, cover NO_REGS
a1 (r52,l0) best GR_REGS, cover GR_REGS
a2 (r50,l0) best GR_REGS, cover GR_REGS
a11 (r48,l0) best GR_REGS, cover GR_REGS
a4 (r46,l0) best GR_REGS, cover GR_REGS
a6 (r45,l0) best GR_REGS, cover GR_REGS
a8 (r44,l0) best GR_REGS, cover GR_REGS
a10 (r43,l0) best GR_REGS, cover GR_REGS
a0(r62,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:4000,4000 MEM:8000
a1(r52,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:4000,4000 MEM:8000
a2(r50,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:12000,12000 MEM:24000
a3(r59,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:4000,4000 MEM:8000
a4(r46,l0) costs: TWIN_REGS:0,0 GR_REGS:0,0 VECTOR_REGS:6000,6000 MEM:12000
a5(r57,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:4000,4000 MEM:8000
a6(r45,l0) costs: TWIN_REGS:0,0 GR_REGS:0,0 VECTOR_REGS:6000,6000 MEM:12000
a7(r55,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:4000,4000 MEM:8000
a8(r44,l0) costs: TWIN_REGS:0,0 GR_REGS:0,0 VECTOR_REGS:6000,6000 MEM:12000
a9(r53,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:4000,4000 MEM:8000
a10(r43,l0) costs: TWIN_REGS:0,0 GR_REGS:0,0 VECTOR_REGS:6000,6000 MEM:12000
a11(r48,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:4000,4000 MEM:8000
Pass 1 for finding pseudo/allocno costs
r62: preferred GR_REGS, alternative NO_REGS, cover GR_REGS
r59: preferred NO_REGS, alternative NO_REGS, cover NO_REGS
r57: preferred NO_REGS, alternative NO_REGS, cover NO_REGS
r55: preferred NO_REGS, alternative NO_REGS, cover NO_REGS
r53: preferred NO_REGS, alternative NO_REGS, cover NO_REGS
r52: preferred GR_REGS, alternative NO_REGS, cover GR_REGS
r50: preferred GR_REGS, alternative NO_REGS, cover GR_REGS
r48: preferred GR_REGS, alternative NO_REGS, cover GR_REGS
r46: preferred GR_REGS, alternative NO_REGS, cover GR_REGS
r45: preferred GR_REGS, alternative NO_REGS, cover GR_REGS
r44: preferred GR_REGS, alternative NO_REGS, cover GR_REGS
r43: preferred GR_REGS, alternative NO_REGS, cover GR_REGS
a0(r62,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:4000,4000 MEM:8000
a1(r52,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:4000,4000 MEM:8000
a2(r50,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:12000,12000 MEM:24000
a3(r59,l0) costs: PTR_REGS:4000,4000 TWIN_REGS:4000,4000 GR_REGS:4000,4000
VECTOR_REGS:8000,8000 MEM:12000
a4(r46,l0) costs: TWIN_REGS:0,0 GR_REGS:0,0 VECTOR_REGS:6000,6000 MEM:12000
a5(r57,l0) costs: PTR_REGS:4000,4000 TWIN_REGS:4000,4000 GR_REGS:4000,4000
VECTOR_REGS:8000,8000 MEM:12000
a6(r45,l0) costs: TWIN_REGS:0,0 GR_REGS:0,0 VECTOR_REGS:6000,6000 MEM:12000
a7(r55,l0) costs: PTR_REGS:4000,4000 TWIN_REGS:4000,4000 GR_REGS:4000,4000
VECTOR_REGS:8000,8000 MEM:12000
a8(r44,l0) costs: TWIN_REGS:0,0 GR_REGS:0,0 VECTOR_REGS:6000,6000 MEM:12000
a9(r53,l0) costs: PTR_REGS:4000,4000 TWIN_REGS:4000,4000 GR_REGS:4000,4000
VECTOR_REGS:8000,8000 MEM:12000
a10(r43,l0) costs: TWIN_REGS:0,0 GR_REGS:0,0 VECTOR_REGS:6000,6000 MEM:12000
a11(r48,l0) costs: PTR_REGS:0,0 TWIN_REGS:0,0 GR_REGS:0,0
VECTOR_REGS:4000,4000 MEM:8000
Insn 47(l0): point = 0
Insn 46(l0): point = 2
Insn 45(l0): point = 4
Insn 44(l0): point = 6
Insn 35(l0): point = 8
Insn 32(l0): point = 10
Insn 51(l0): point = 12
Insn 40(l0): point = 14
Insn 34(l0): point = 16
Insn 29(l0): point = 18
Insn 26(l0): point = 20
Insn 28(l0): point = 22
Insn 25(l0): point = 24
Insn 23(l0): point = 26
Insn 20(l0): point = 28
Insn 22(l0): point = 30
Insn 19(l0): point = 32
Insn 17(l0): point = 34
Insn 14(l0): point = 36
Insn 16(l0): point = 38
Insn 13(l0): point = 40
Insn 11(l0): point = 42
Insn 6(l0): point = 44
Insn 4(l0): point = 46
Insn 7(l0): point = 48
Insn 2(l0): point = 50
Insn 43(l0): point = 52
a0(r62): [3..52]
a1(r52): [9..48]
a2(r50): [9..44]
a3(r59): [11..12]
a4(r46 [0]): [11..18]
a4(r46 [1]): [11..18]
a5(r57): [21..24]
a6(r45 [0]): [21..26]
a6(r45 [1]): [21..26]
a7(r55): [29..32]
a8(r44 [0]): [29..34]
a8(r44 [1]): [29..34]
a9(r53): [37..40]
a10(r43 [0]): [37..42]
a10(r43 [1]): [37..42]
a11(r48): [45..46]
Compressing live ranges: from 55 to 10 - 18%
Ranges after the compression:
a0(r62): [0..9]
a1(r52): [0..9]
a2(r50): [0..7]
a3(r59): [0..1]
a4(r46 [0]): [0..1]
a4(r46 [1]): [0..1]
a5(r57): [2..3]
a6(r45 [0]): [2..3]
a6(r45 [1]): [2..3]
a7(r55): [4..5]
a8(r44 [0]): [4..5]
a8(r44 [1]): [4..5]
a9(r53): [6..7]
a10(r43 [0]): [6..7]
a10(r43 [1]): [6..7]
a11(r48): [8..9]
+++Allocating 96 bytes for conflict table (uncompressed size 128)
;; a0(r62,l0) conflicts: a4(r46,w0,l0) a4(r46,w1,l0) a2(r50,l0) a1(r52,l0)
a6(r45,w0,l0) a6(r45,w1,l0) a8(r44,w0,l0) a8(r44,w1,l0) a10(r43,w0,l0)
a10(r43,w1,l0) a11(r48,l0)
;; total conflict hard regs: 0
;; conflict hard regs: 0
;; a1(r52,l0) conflicts: a4(r46,w0,l0) a4(r46,w1,l0) a2(r50,l0) a0(r62,l0)
a6(r45,w0,l0) a6(r45,w1,l0) a8(r44,w0,l0) a8(r44,w1,l0) a10(r43,w0,l0)
a10(r43,w1,l0) a11(r48,l0)
;; total conflict hard regs: 0
;; conflict hard regs: 0
;; a2(r50,l0) conflicts: a4(r46,w0,l0) a4(r46,w1,l0) a0(r62,l0) a1(r52,l0)
a6(r45,w0,l0) a6(r45,w1,l0) a8(r44,w0,l0) a8(r44,w1,l0) a10(r43,w0,l0)
a10(r43,w1,l0)
;; total conflict hard regs: 0
;; conflict hard regs: 0
;; a3(r59,l0) conflicts:;; a4(r46,l0) conflicts:
;; subobject 0: a2(r50,l0) a0(r62,l0) a1(r52,l0)
;; total conflict hard regs: 0
;; conflict hard regs: 0
;; subobject 1: a2(r50,l0) a0(r62,l0) a1(r52,l0)
;; total conflict hard regs: 0
;; conflict hard regs: 0
;; a5(r57,l0) conflicts:;; a6(r45,l0) conflicts:
;; subobject 0: a2(r50,l0) a0(r62,l0) a1(r52,l0)
;; total conflict hard regs:
;; conflict hard regs:
;; subobject 1: a2(r50,l0) a0(r62,l0) a1(r52,l0)
;; total conflict hard regs:
;; conflict hard regs:
;; a7(r55,l0) conflicts:;; a8(r44,l0) conflicts:
;; subobject 0: a2(r50,l0) a0(r62,l0) a1(r52,l0)
;; total conflict hard regs:
;; conflict hard regs:
;; subobject 1: a2(r50,l0) a0(r62,l0) a1(r52,l0)
;; total conflict hard regs:
;; conflict hard regs:
;; a9(r53,l0) conflicts:;; a10(r43,l0) conflicts:
;; subobject 0: a2(r50,l0) a0(r62,l0) a1(r52,l0)
;; total conflict hard regs:
;; conflict hard regs:
;; subobject 1: a2(r50,l0) a0(r62,l0) a1(r52,l0)
;; total conflict hard regs:
;; conflict hard regs:
;; a11(r48,l0) conflicts: a0(r62,l0) a1(r52,l0)
;; total conflict hard regs:
;; conflict hard regs:
cp0:a2(r50)<->a11(r48)@125:shuffle
regions=1, blocks=3, points=10
allocnos=12 (big 4), copies=1, conflicts=0, ranges=16
**** Allocnos coloring:
Loop 0 (parent -1, header bb0, depth 0)
bbs: 2
all: 0r62 1r52 2r50 3r59 4r46 5r57 6r45 7r55 8r44 9r53 10r43 11r48
modified regnos: 43 44 45 46 48 50 52 53 55 57 59 62
border:
Pressure: GR_REGS=6
Reg 62 of GR_REGS has 1 regs less
Reg 52 of GR_REGS has 1 regs less
Reg 50 of GR_REGS has 1 regs less
Spill a3(r59,l0)
Reg 46 of GR_REGS has 7 regs less
Spill a5(r57,l0)
Reg 45 of GR_REGS has 6 regs less
Spill a7(r55,l0)
Reg 44 of GR_REGS has 6 regs less
Spill a9(r53,l0)
Reg 43 of GR_REGS has 6 regs less
Pushing a11(r48,l0)
Pushing a10(r43,l0)
Pushing a8(r44,l0)
Pushing a6(r45,l0)
Pushing a0(r62,l0)(potential spill: pri=571, cost=8000)
Pushing a1(r52,l0)
Pushing a2(r50,l0)
Pushing a4(r46,l0)
Popping a4(r46,l0) -- assign reg 4
Popping a2(r50,l0) -- assign reg 3
Popping a1(r52,l0) -- assign reg 2
Popping a0(r62,l0) -- assign reg 1
Popping a6(r45,l0) -- assign reg 4
Popping a8(r44,l0) -- assign reg 4
Popping a10(r43,l0) -- assign reg 4
Popping a11(r48,l0) -- assign reg 3
Disposition:
10:r43 l0 4 8:r44 l0 4 6:r45 l0 4 4:r46 l0 4
11:r48 l0 3 2:r50 l0 3 1:r52 l0 2 9:r53 l0 mem
7:r55 l0 mem 5:r57 l0 mem 3:r59 l0 mem 0:r62 l0 1
New iteration of spill/restore move
+++Costs: overall 48000, reg 0, mem 48000, ld 0, st 0, move 0
+++ move loops 0, new jumps 0
insn=43, live_throughout: 0, 13, dead_or_set: 62
insn=2, live_throughout: 0, 62, dead_or_set:
insn=7, live_throughout: 13, 62, dead_or_set: 0, 52
insn=4, live_throughout: 13, 52, 62, dead_or_set: 48
insn=6, live_throughout: 13, 52, 62, dead_or_set: 48, 50
insn=11, live_throughout: 13, 50, 52, 62, dead_or_set: 43
insn=12, live_throughout: 13, 43, 50, 52, 62, dead_or_set:
insn=13, live_throughout: 13, 43, 50, 52, 62, dead_or_set: 53
insn=16, live_throughout: 13, 43, 50, 52, 53, 62, dead_or_set:
insn=14, live_throughout: 13, 50, 52, 62, dead_or_set: 43, 53
insn=17, live_throughout: 13, 50, 52, 62, dead_or_set: 44
insn=18, live_throughout: 13, 44, 50, 52, 62, dead_or_set:
insn=19, live_throughout: 13, 44, 50, 52, 62, dead_or_set: 55
insn=22, live_throughout: 13, 44, 50, 52, 55, 62, dead_or_set:
insn=20, live_throughout: 13, 50, 52, 62, dead_or_set: 44, 55
insn=23, live_throughout: 13, 50, 52, 62, dead_or_set: 45
insn=24, live_throughout: 13, 45, 50, 52, 62, dead_or_set:
insn=25, live_throughout: 13, 45, 50, 52, 62, dead_or_set: 57
insn=28, live_throughout: 13, 45, 50, 52, 57, 62, dead_or_set:
insn=26, live_throughout: 13, 50, 52, 62, dead_or_set: 45, 57
insn=29, live_throughout: 13, 50, 52, 62, dead_or_set: 46
insn=30, live_throughout: 13, 46, 50, 52, 62, dead_or_set:
insn=34, live_throughout: 13, 46, 50, 52, 62, dead_or_set:
insn=40, live_throughout: 13, 46, 50, 52, 62, dead_or_set: 0
insn=51, live_throughout: 0, 13, 46, 50, 52, 62, dead_or_set: 59
insn=32, live_throughout: 0, 13, 50, 52, 62, dead_or_set: 46, 59
insn=35, live_throughout: 0, 13, 62, dead_or_set: 50, 52
insn=44, live_throughout: 0, 13, 62, dead_or_set:
insn=45, live_throughout: 0, 13, 62, dead_or_set:
insn=46, live_throughout: 0, dead_or_set: 62
insn=47, live_throughout: 0, 13, dead_or_set:
init_insns for 53: (insn_list:REG_DEP_TRUE 13 (nil))
init_insns for 55: (insn_list:REG_DEP_TRUE 19 (nil))
init_insns for 57: (insn_list:REG_DEP_TRUE 25 (nil))
init_insns for 59: (insn_list:REG_DEP_TRUE 51 (nil))
changing reg in insn 11
changing reg in insn 16
changing reg in insn 14
changing reg in insn 12
changing reg in insn 17
changing reg in insn 22
changing reg in insn 20
changing reg in insn 18
changing reg in insn 23
changing reg in insn 28
changing reg in insn 26
changing reg in insn 24
changing reg in insn 29
changing reg in insn 34
changing reg in insn 32
changing reg in insn 30
changing reg in insn 4
changing reg in insn 6
changing reg in insn 6
changing reg in insn 34
changing reg in insn 28
changing reg in insn 22
changing reg in insn 16
changing reg in insn 35
changing reg in insn 7
changing reg in insn 35
changing reg in insn 43
changing reg in insn 46
Spilling for insn 16.
Spilling for insn 14.
Using reg 0 for reload 0
Spilling for insn 22.
Spilling for insn 20.
Using reg 0 for reload 0
Spilling for insn 28.
Spilling for insn 26.
Using reg 0 for reload 0
Spilling for insn 34.
Spilling for insn 32.
Spilling for insn 35.
Using reg 20 for reload 1
Spilling for insn 16.
Spilling for insn 14.
Using reg 0 for reload 0
Spilling for insn 22.
Spilling for insn 20.
Using reg 0 for reload 0
Spilling for insn 28.
Spilling for insn 26.
Using reg 0 for reload 0
Spilling for insn 34.
Spilling for insn 32.
Spilling for insn 35.
Using reg 20 for reload 1
deleting insn with uid = 13.
deleting insn with uid = 19.
deleting insn with uid = 25.
deleting insn with uid = 51.
Reloads for insn # 16
Reload 0: reload_out (SI) = (mem/s/c:SI (reg/f:HI 3 R3 [50]) [0
x.cmplx_elements+0 S4 A128])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/s/c:SI (reg/f:HI 3 R3 [50]) [0 x.cmplx_elements+0
S4 A128])
Reloads for insn # 14
Reload 0: reload_in (HI) = (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 12 [0xc]))
GR_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0), can't combine
reload_in_reg: (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 12 [0xc]))
reload_reg_rtx: (reg:HI 0 R0)
Reload 1: reload_out (SI) = (mem/s/c:SI (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 12 [0xc]))
[0 MEM[(struct complex16 *)&D.2118].rawValue+0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/s/c:SI (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 12 [0xc]))
[0 MEM[(struct complex16 *)&D.2118].rawValue+0 S4 A32])
Reloads for insn # 22
Reload 0: reload_out (SI) = (mem/s/c:SI (plus:HI (reg/f:HI 3 R3 [50])
(const_int 4 [0x4])) [0
x.cmplx_elements+4 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/s/c:SI (plus:HI (reg/f:HI 3 R3 [50])
(const_int 4 [0x4])) [0
x.cmplx_elements+4 S4 A32])
Reloads for insn # 20
Reload 0: reload_in (HI) = (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 8 [0x8]))
GR_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0), can't combine
reload_in_reg: (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 8 [0x8]))
reload_reg_rtx: (reg:HI 0 R0)
Reload 1: reload_out (SI) = (mem/s/c:SI (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 8 [0x8])) [0
MEM[(struct complex16 *)&D.2123].rawValue+0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/s/c:SI (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 8 [0x8])) [0
MEM[(struct complex16 *)&D.2123].rawValue+0 S4 A32])
Reloads for insn # 28
Reload 0: reload_out (SI) = (mem/s/c:SI (plus:HI (reg/f:HI 3 R3 [50])
(const_int 8 [0x8])) [0
x.cmplx_elements+8 S4 A64])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/s/c:SI (plus:HI (reg/f:HI 3 R3 [50])
(const_int 8 [0x8])) [0
x.cmplx_elements+8 S4 A64])
Reloads for insn # 26
Reload 0: reload_in (HI) = (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 4 [0x4]))
GR_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0), can't combine
reload_in_reg: (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 4 [0x4]))
reload_reg_rtx: (reg:HI 0 R0)
Reload 1: reload_out (SI) = (mem/s/c:SI (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 4 [0x4])) [0
MEM[(struct complex16 *)&D.2128].rawValue+0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/s/c:SI (plus:HI (reg/f:HI 18 pseudoFP)
(const_int 4 [0x4])) [0
MEM[(struct complex16 *)&D.2128].rawValue+0 S4 A32])
Reloads for insn # 34
Reload 0: reload_out (SI) = (mem/s/c:SI (plus:HI (reg/f:HI 3 R3 [50])
(const_int 12 [0xc]))
[0 x.cmplx_elements+12 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/s/c:SI (plus:HI (reg/f:HI 3 R3 [50])
(const_int 12 [0xc]))
[0 x.cmplx_elements+12 S4 A32])
Reloads for insn # 32
Reload 0: reload_out (SI) = (mem/s/c:SI (reg/f:HI 18 pseudoFP) [0 MEM[(struct
complex16 *)&D.2133].rawValue+0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/s/c:SI (reg/f:HI 18 pseudoFP) [0 MEM[(struct
complex16 *)&D.2133].rawValue+0 S4 A32])
Reloads for insn # 35
Reload 0: reload_out (V8HI) = (mem:V8HI (reg/v/f:HI 2 R2 [orig:52 a ] [52]) [6
*a_2(D)+0 S16 A128])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem:V8HI (reg/v/f:HI 2 R2 [orig:52 a ] [52]) [6
*a_2(D)+0 S16 A128])
Reload 1: reload_in (V8HI) = (mem/s/c:V8HI (reg/f:HI 3 R3 [50]) [0
x.all_elements+0 S16 A128])
VECTOR_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (mem/s/c:V8HI (reg/f:HI 3 R3 [50]) [0 x.all_elements+0
S16 A128])
reload_reg_rtx: (reg:V8HI 20 V0)
try_optimize_cfg iteration 1
starting the processing of deferred insns
ending the processing of deferred insns
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue:n_basic_blocks 3 n_edges 2 count 3 ( 1)
df_worklist_dataflow_doublequeue:n_basic_blocks 3 n_edges 2 count 3 ( 1)
fn1
Dataflow summary:
;; invalidated by call 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 12
[R12] 17 [pseudoCC] 20 [V0] 21 [V1] 22 [V2] 23 [V3] 24 [V4] 25 [V5] 26 [V6] 27
[V7] 28 [V8] 29 [V9] 30 [V10] 31 [V11] 32 [V12] 33 [V13] 34 [V14] 35 [V15]
;; hardware regs used 13 [FP]
;; regular block artificial uses 13 [FP] 18 [pseudoFP]
;; eh block artificial uses 13 [FP] 18 [pseudoFP] 19 [pseudoAP]
;; entry block defs 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 12 [R12] 13
[FP] 18 [pseudoFP]
;; exit block uses 0 [R0] 13 [FP] 18 [pseudoFP]
;; regs ever live 0[R0] 1[R1] 2[R2] 3[R3] 4[R4] 5[R5] 13[FP]
17[pseudoCC] 18[pseudoFP] 19[pseudoAP] 20[V0]
;; ref usage r0={5d,6u} r1={2d,1u} r2={2d,1u} r3={3d,6u} r4={5d,12u}
r5={5d,12u} r12={1d} r13={3d,8u} r17={3d} r18={1d,6u} r20={1d,1u}
;; total ref usage 84{31d,53u,0e} in 31{31 regular + 0 call} insns.
(note 1 0 9 NOTE_INSN_DELETED)
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(13){ }u-1(18){ }}
;; lr in 0 [R0] 13 [FP] 18 [pseudoFP]
;; lr use 0 [R0] 13 [FP] 18 [pseudoFP]
;; lr def 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 13 [FP] 17
[pseudoCC] 20 [V0]
;; live in 0 [R0] 13 [FP] 18 [pseudoFP]
;; live gen 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 13 [FP] 20 [V0]
;; live kill 17 [pseudoCC]
;; Pred edge ENTRY [100.0%] (fallthru)
(note 9 1 5 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 5 9 8 2 NOTE_INSN_DELETED)
(note 8 5 36 2 NOTE_INSN_FUNCTION_BEG)
(note 36 8 43 2 NOTE_INSN_DELETED)
(insn 43 36 2 2 (set (reg/f:HI 1 R1 [62])
(reg/f:HI 13 FP)) test.c:37 15 {movhi}
(nil))
(insn 2 43 7 2 (parallel [
(set (reg/f:HI 13 FP)
(plus:HI (reg/f:HI 13 FP)
(const_int -32 [0xffffffffffffffe0])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:29 24 {addhi3}
(nil))
(insn 7 2 4 2 (set (reg/v/f:HI 2 R2 [orig:52 a ] [52])
(reg:HI 0 R0 [ a ])) test.c:29 15 {movhi}
(nil))
(insn 4 7 6 2 (parallel [
(set (reg/f:HI 3 R3 [48])
(plus:HI (reg/f:HI 13 FP)
(const_int 15 [0xf])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:29 24 {addhi3}
(nil))
(insn 6 4 11 2 (parallel [
(set (reg/f:HI 3 R3 [50])
(and:HI (reg/f:HI 3 R3 [48])
(const_int -16 [0xfffffffffffffff0])))
(clobber (reg:CC 17 pseudoCC))
]) test.c:29 58 {andhi3}
(nil))
(insn 11 6 12 2 (set (reg:SI 4 R4 [orig:43 D.2119 ] [43])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 81 {commsGet}
(expr_list:REG_EQUIV (unspec_volatile:SI [
(const_int 1 [0x1])
] 8)
(nil)))
(debug_insn 12 11 13 2 (var_location:SI converter$rawValue (reg:SI 4 R4
[orig:43 D.2119 ] [43])) test.c:17 -1
(nil))
(note 13 12 16 2 NOTE_INSN_DELETED)
(insn 16 13 53 2 (set (mem/s/c:SI (reg/f:HI 3 R3 [50]) [0 x.cmplx_elements+0 S4
A128])
(reg:SI 4 R4 [orig:43 D.2119 ] [43])) test.c:18 16 {movsi}
(nil))
(insn 53 16 14 2 (set (reg:HI 0 R0)
(plus:HI (reg/f:HI 18 pseudoFP)
(const_int 12 [0xc]))) test.c:18 31 {*lea_add}
(nil))
(insn 14 53 17 2 (set (mem/s/c:SI (reg:HI 0 R0) [0 MEM[(struct complex16
*)&D.2118].rawValue+0 S4 A32])
(reg:SI 4 R4 [orig:43 D.2119 ] [43])) test.c:18 16 {movsi}
(nil))
(insn 17 14 18 2 (set (reg:SI 4 R4 [orig:44 D.2124 ] [44])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 81 {commsGet}
(expr_list:REG_EQUIV (unspec_volatile:SI [
(const_int 1 [0x1])
] 8)
(nil)))
(debug_insn 18 17 19 2 (var_location:SI converter$rawValue (reg:SI 4 R4
[orig:44 D.2124 ] [44])) test.c:17 -1
(nil))
(note 19 18 22 2 NOTE_INSN_DELETED)
(insn 22 19 54 2 (set (mem/s/c:SI (plus:HI (reg/f:HI 3 R3 [50])
(const_int 4 [0x4])) [0 x.cmplx_elements+4 S4 A32])
(reg:SI 4 R4 [orig:44 D.2124 ] [44])) test.c:18 16 {movsi}
(nil))
(insn 54 22 20 2 (set (reg:HI 0 R0)
(plus:HI (reg/f:HI 18 pseudoFP)
(const_int 8 [0x8]))) test.c:18 31 {*lea_add}
(nil))
(insn 20 54 23 2 (set (mem/s/c:SI (reg:HI 0 R0) [0 MEM[(struct complex16
*)&D.2123].rawValue+0 S4 A32])
(reg:SI 4 R4 [orig:44 D.2124 ] [44])) test.c:18 16 {movsi}
(nil))
(insn 23 20 24 2 (set (reg:SI 4 R4 [orig:45 D.2129 ] [45])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 81 {commsGet}
(expr_list:REG_EQUIV (unspec_volatile:SI [
(const_int 1 [0x1])
] 8)
(nil)))
(debug_insn 24 23 25 2 (var_location:SI converter$rawValue (reg:SI 4 R4
[orig:45 D.2129 ] [45])) test.c:17 -1
(nil))
(note 25 24 28 2 NOTE_INSN_DELETED)
(insn 28 25 55 2 (set (mem/s/c:SI (plus:HI (reg/f:HI 3 R3 [50])
(const_int 8 [0x8])) [0 x.cmplx_elements+8 S4 A64])
(reg:SI 4 R4 [orig:45 D.2129 ] [45])) test.c:18 16 {movsi}
(nil))
(insn 55 28 26 2 (set (reg:HI 0 R0)
(plus:HI (reg/f:HI 18 pseudoFP)
(const_int 4 [0x4]))) test.c:18 31 {*lea_add}
(nil))
(insn 26 55 29 2 (set (mem/s/c:SI (reg:HI 0 R0) [0 MEM[(struct complex16
*)&D.2128].rawValue+0 S4 A32])
(reg:SI 4 R4 [orig:45 D.2129 ] [45])) test.c:18 16 {movsi}
(nil))
(insn 29 26 30 2 (set (reg:SI 4 R4 [orig:46 D.2134 ] [46])
(unspec_volatile:SI [
(const_int 1 [0x1])
] 8)) test.c:17 81 {commsGet}
(expr_list:REG_EQUIV (unspec_volatile:SI [
(const_int 1 [0x1])
] 8)
(nil)))
(debug_insn 30 29 34 2 (var_location:SI converter$rawValue (reg:SI 4 R4
[orig:46 D.2134 ] [46])) test.c:17 -1
(nil))
(insn 34 30 40 2 (set (mem/s/c:SI (plus:HI (reg/f:HI 3 R3 [50])
(const_int 12 [0xc])) [0 x.cmplx_elements+12 S4 A32])
(reg:SI 4 R4 [orig:46 D.2134 ] [46])) test.c:18 16 {movsi}
(nil))
(insn 40 34 51 2 (set (reg/i:HI 0 R0)
(const_int 5 [0x5])) test.c:37 15 {movhi}
(expr_list:REG_EQUAL (const_int 5 [0x5])
(nil)))
(note 51 40 32 2 NOTE_INSN_DELETED)
(insn 32 51 56 2 (set (mem/s/c:SI (reg/f:HI 18 pseudoFP) [0 MEM[(struct
complex16 *)&D.2133].rawValue+0 S4 A32])
(reg:SI 4 R4 [orig:46 D.2134 ] [46])) test.c:18 16 {movsi}
(nil))
(insn 56 32 35 2 (set (reg:V8HI 20 V0)
(mem/s/c:V8HI (reg/f:HI 3 R3 [50]) [0 x.all_elements+0 S16 A128]))
test.c:35 92 {movv8hi_loadstore}
(nil))
(insn 35 56 44 2 (set (mem:V8HI (reg/v/f:HI 2 R2 [orig:52 a ] [52]) [6
*a_2(D)+0 S16 A128])
(reg:V8HI 20 V0)) test.c:35 92 {movv8hi_loadstore}
(nil))
(insn 44 35 45 2 (clobber (mem:BLK (scratch) [0 A8])) test.c:37 -1
(nil))
(insn 45 44 46 2 (clobber (mem:BLK (reg/f:HI 13 FP) [0 A8])) test.c:37 -1
(nil))
(insn 46 45 47 2 (set (reg/f:HI 13 FP)
(reg/f:HI 1 R1 [62])) test.c:37 15 {movhi}
(nil))
(insn 47 46 50 2 (use (reg/i:HI 0 R0)) test.c:37 -1
(nil))
;; End of basic block 2 -> ( 1)
;; lr out 0 [R0] 13 [FP] 18 [pseudoFP]
;; live out 0 [R0] 13 [FP] 18 [pseudoFP]
;; Succ edge EXIT [100.0%] (fallthru)
(note 50 47 52 NOTE_INSN_DELETED)
(note 52 50 0 NOTE_INSN_DELETED)
