2011/3/20 Georg-Johann Lay <a...@gjlay.de>:
> The AVR controller basically has two kinds of hard registers:
>
> * LD_REGS (constraint "d") that can move immediates
> * NO_LD_REGS (constraint "l") that cannot move immediates
>
> movsi insn of avr backend does not supply an "l,i" constraint alternative,
> so that reload takes care of that and allocates an intermediate SImode
> d-reg.
The *movsi pattern:
(define_insn "*movsi"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
(match_operand:SI 1 "general_operand" "r,L,Qm,rL,i,i"))]
Last constraints pair `r' and `i' supply an `l' and `i' because `r' = `dl'.
Also, to optimize movsi exists the following peephole2:
(define_peephole2 ; movsi_lreg_const
[(match_scratch:QI 2 "d")
(set (match_operand:SI 0 "l_register_operand" "")
(match_operand:SI 1 "immediate_operand" ""))
(match_dup 2)]
"(operands[1] != const0_rtx
&& operands[1] != constm1_rtx)"
[(parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))])]
"")
>
> The drawback is that this allocates 4 GPRs (AVR is 8-bit machine).
Please, provide an example.
Denis.
