On Fri, 11 Feb 2011, Bernd Schmidt wrote:
> Suppose I have two insns, one reserving (A|B|C), and the other reserving > A. I'm observing that when the first one is scheduled in an otherwise > empty state, it reserves the A unit and blocks the second one from being > scheduled in the same cycle. This is a problem when there's an > anti-dependence of cost 0 between the two instructions. > > Vlad - two questions. Is this behaviour what you would expect to happen, > and how much work do you think would be involved to fix it (i.e. make > the first one transition to a state where we can still reserve any two > out of the three units)? Could you please clarify a bit: would the modified behavior match what your target CPU does? The current behavior matches CPUs without lookahead in instruction dispatch: the first insn goes to the first matching execution unit (A), the second has to wait. Alexander
