Re: Is eliminate_regs_in_insn allowed to generate invalid instruction?

[Ian Lance Taylor]

"Bingfeng Mei" <b...@broadcom.com> writes:

> from gen_reload function. 
>   /* Otherwise, just write (set OUT IN) and hope for the best.  */
>   else
>     emit_insn (gen_rtx_SET (VOIDmode, out, in));

Those lines are one of the curses of reload.  When you hit them, you
know something has gone wrong.  Unfortunately, exactly what has gone
wrong can be difficult to determine.  It basically means that you are
trying to reload something that the reload pass does not understand.


> The comment doesn’t sound very convincing to me. 
>
>
> From debug message:
> Reloads for insn # 680
> Reload 0: reload_in (SI) = (plus:SI (reg/f:SI 57 r57)
>                                                     (const_int 40 [0x28]))
>       GR_REGS, RELOAD_FOR_INPUT_ADDRESS (opnum = 1)
>       reload_in_reg: (plus:SI (reg/f:SI 57 r57)
>                                                     (const_int 40 [0x28]))
>       reload_reg_rtx: (reg:SI 4 r4)
> Reload 1: reload_in (SI) = (plus:SI (reg/f:SI 57 r57)
>                                                     (const_int 78396 
> [0x1323c]))
>       GR_REGS, RELOAD_FOR_INPUT_ADDRESS (opnum = 1), can't combine
>       reload_in_reg: (plus:SI (reg/f:SI 57 r57)
>                                                     (const_int 78396 
> [0x1323c]))
>       reload_reg_rtx: (reg:SI 6 r6)
> Reload 2: reload_in (SI) = (mem/c:SI (plus:SI (reg/f:SI 57 r57)
>                                                         (const_int 78396 
> [0x1323c])) [50 %sfp+78252 S4 A32])
>       GR_REGS, RELOAD_FOR_INPUT_ADDRESS (opnum = 1), can't combine
>       reload_in_reg: (reg:SI 596 [ ivtmp.474 ])
>       reload_reg_rtx: (reg:SI 9 r9)
> Reload 3: reload_in (SI) = (plus:SI (mult:SI (reg:SI 596 [ ivtmp.474 ])
>                                                         (const_int 8 [0x8]))
>                                                     (plus:SI (reg/f:SI 57 r57)
>                                                         (const_int 40 
> [0x28])))
>       GR_REGS, RELOAD_FOR_INPUT (opnum = 1), inc by 8
>       reload_in_reg: (plus:SI (mult:SI (reg:SI 596 [ ivtmp.474 ])
>                                                         (const_int 8 [0x8]))
>                                                     (plus:SI (reg/f:SI 57 r57)
>                                                         (const_int 40 
> [0x28])))
>       reload_reg_rtx: (reg:SI 4 r4)
>
>
> I don’t understand why Reload 3 is necessary. After reload 0, 1, 2, 
> The following expression already fits into our addressing mode. 
>
> (plus:SI (mult:SI (reg:SI 9 r9)  (const_int 8 [0x8]))
>                                  (reg:SI 4 r4))
>
> Instead GCC tries to generate invalid 
> (insn 1716 1715 680 84 src/weighted_prediction.c:729 (set (reg:SI 4 r4)
>         (plus:SI (mult:SI (reg:SI 9 r9)
>                 (const_int 8 [0x8]))
>             (reg:SI 4 r4))) -1 (nil))
> and load from [r4] subsequently. 

Sounds like you're well on the way to tracking down the problem: you
need to see why gcc decided to add reload 3 given the existence of the
reloads 0 through 2.  In particular, look at the code after
  if (strict_memory_address_addr_space_p (mode, ad, as))
in find_reloads_address.

Ian