Hi,
I am facing a strange behaviour with secondary reload in gcc43.
I have a type of register that can load and store from virtually anything
else, lets call the class CHIP_REGS, meaning it has no need for reload.
However, if I get an input reload for ALL_REGS then I assume the worst
case scenario and provide reload code for operations in a certain mode.
So my secondary reload has the following shape:
if(rclass == CHIP_REGS)
return NO_REGS;
else if(...)
{
}
else if(mode == HImode)
{
if(in_p)
sri->icode = CODE_FOR_movhi_via_chipreg_in;
else
sri->icode = CODE_FOR_movhi_via_chipreg_out;
return NO_REGS;
}
...
The movhi_via_chipreg_in assumes with constraints that neither source nor
destination of the move is CHIP_REGS because that doesn't need a reload.
However, I get a reload_in for ALL_REGS, I assume worst case scenario and
forward secondary reload to movhi_via_chipreg_in and then the register is
allocated to a CHIP_REGS and fails to match constraints of
movhi_via_chipreg_in. Here's what I get in gregs:
Reloads for insn # 164
Reload 0: CHIP_REGS, RELOAD_FOR_INPUT_ADDRESS (opnum = 0), can't combine,
secondary_reload_p
reload_reg_rtx: (reg:QI 1 AL)
Reload 1: reload_in (HI) = (reg/v:HI 32 [ hx ])
ALL_REGS, RELOAD_FOR_INPUT (opnum = 0)
reload_in_reg: (reg/v:HI 32 [ hx ])
reload_reg_rtx: (reg:HI 0 AH)
secondary_in_reload = 0
secondary_in_icode = movhi_via_chipreg_in
AH is a register in CHIP_REG. Then I get the following in output:
e_fmod.i:80: error: insn does not satisfy its constraints:
(insn 677 548 164 8 e_fmod.i:33 (parallel [
(set (reg:HI 0 AH)
(mem/c:HI (plus:QI (reg/f:QI 6 Y)
(const_int 16 [0x10])) [0 hx+0 S2 A16]))
(clobber (reg:QI 1 AL))
]) 10 {movhi_via_chipreg_in} (nil))
e_fmod.i:80: internal compiler error: in reload_cse_simplify_operands, at
postreload.c:395
The insn
(set (reg:HI 0 AH)
(mem/c:HI (plus:QI (reg/f:QI 6 Y)
(const_int 16 [0x10])) [0 hx+0 S2 A16]))
doesn't need a scratch register at all.
I wonder what's the best way to deal with it. Any suggestions?
Cheers,
--
PMatos
