Hi -- I'm working with a processor which sets the condition bits when a NaN is used as an operand in a compare in a way which is the same as a valid ordered compare. There is a flag bit which is set for a NaN compare, but it may also be set in a non-NaN compare.
float a = 1.0, b = 2.0, x = NaN; (a < b) generates the same condition flags as (a < x). IEEE std requires all comparisons involving a NaN to fail (or trap). Are there other processors which do this? How do they handle generating IEEE std compliant code? A related problem is that CSE will optimize FP comparisons and garble the result. (This doesn't happen with soft-fp.) int r = 0, s = 0; float a = 1.0, x = NaN; r = (a <= x); s = (a > x); should result in r == s == 0. CSE translates this (more or less) into r = (a <= x); s = !r; Is there a way to prevent CSE from optimizing FP comparisons? -- Michael Eager ea...@eagercon.com 1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
