On 06/22/10 08:52, Revital1 Eres wrote:
Hello,I have a question regarding code generation for a new target I'm working on. I am using GCC 4.6. In reload pass the following first instruction is replaced with the second one after spilling reg 182 to the stack. The problem is that the generated new instruction does not have a valid address format and I'm not sure why it was considered as a valid replacement. Any help on how to resolve this is appreciated. (insn 282 150 151 13 jctrans.c:109 (set (reg:SI 12 r12) (mem/s:SI (plus:SI (reg/v/f:SI 182 [ incomp ]) (const_int 8 [0x8])) [6 *incomp_85 S4 A32])) -1 (nil)) (insn 282 150 151 13 jctrans.c:109 (set (reg:SI 12 r12) (mem/s:SI (plus:SI (mem/c:SI (plus:SI (reg/f:SI 63 r63) (const_int -12 [0xfffffff4])) [56 %sfp+-12 S4 A32]) (const_int 8 [0x8])) [6 *incomp_85 S4 A32])) -1 (nil))
What's happening is pseudo 182 is not getting a hard reg, and is thus on the stack (see reg_equiv_mem). Reload will substitute the MEM for the unassigned pseudo.
Check your GO_IF_LEGITIMATE_ADDRESS. You might also look at your REGNO_OK_FOR_BASE_P and whether or not it handles a strict & non-strict variant properly.
Jeff
