I've implemented some special insns that access hardware resources. These insns have side effects so they cannot be deleted or reordered with respect to each other. I made them UNSPEC_VOLATILE, which generates correct code. Unfortunately, performance is poor.
The problem is that UNSPEC_VOLATILE is a scheduling barrier, so the scheduler does not issue any other insn in the same cycle. Since my chip is a VLIW, I rely on the scheduler annotations to determine which insns go in a bundle (same cycle == same bundle). Due to the scheduler barrier, none of these special insns ever get bundled with anything else, which wastes valuable VLIW slots. How should I achieve the effect I need (preserve these insns and their relative ordering), while still allowing other insns to be bundled with them? One hack that occurs to me is to annotate the special insns to pretend each one reads and writes a phony hardware register. This would preserve ordering and prevent them from being deleted, at least if a phony hardware register would be considered live on exit from a function, etc. (would it?) But even if this works, I worry the phony dependencies and more complex insn patterns might prevent 'combine' from ever combining two of these special insns together, which is valuable and works now. But perhaps there is a cleaner way. Any advice? Thanks! -Mat
