On Sun, Jan 24, 2010 at 10:32 PM, Steve White <swh...@aip.de> wrote: > Richard, > > Could you provide us with a good reference for the latencies and other > speed issues of SSE operations? What I've found is scattered and hard > to compare. > > Frankly, I was under the misconception that each of these SSE operatons > was meant to be accomplished in a single clock cycle (although I knew there > are various other issues.)
Both Intel and AMD list them in their optimization and/or instruction reference guides. I suppose wikipedia might even link to the relevant pdfs (though google should also find them). Richard.
