Ian Lance Taylor wrote:
I guess the obvious counterexample would be a processor which supported
vector registers and supported bitfield operations on such registers. I
don't know of any such processors.
The Control Data Cyber 205 (roughly '75-'85).
You could write the inner loop of the Sieve of Eratosthenes as a single
vector instruction.
We do not have a (supported) port for that architecture.
Kind regards,
--
Toon Moene - e-mail: t...@moene.org - phone: +31 346 214290
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