On Tue, May 5, 2009 at 11:04 PM, DJ Delorie <d...@redhat.com> wrote: > I'm working on a coprocessor which has separate SIMD arithmetic > operations for each data size, but only one SIMD logical operation for > all sizes. I.e. there's four ADD insns (V8QI, V4HI, etc) , but only > one AND insn. I'd like to use an opaque vector type for the AND > builtin, to avoid warnings.
You could do what the rs6000 back-end does for the altivec builtins and resolve them while the parser is run (the SPU back-end does the same thing too). Yes there are opaque vector types, you just use build_opaque_vector_type instead of build_vector_type. -- Pinski
