Hi,all,
I have recently porting the instruction scheduler to the new arch of
our lab. But something seems strange.
Our pipeline( single issue) will stall for 1 cycle if the
arithmetic/logic instruction follows by a load, and for 2 cycles if a
store/jump/call instruction follows. I wrote my scheduler as follows:
(define_insn_reservation "apc_genetic_insn" 1
(eq_attr "type" "!load,mul")
"nothing")
(define_insn_reservation "apc_load_insn" 2
(eq_attr "type" "load")
"nothing")
(define_insn_reservation "apc_mul_insn" 4
(eq_attr "type" "mul")
"nothing")
The multiply operation is implemented by 4 arithmetic instruction, so
I made the latency 4 cycles. As our pipeline introduces no interlock,
so the reservations for all insns are "nothing", which is very similar
as XTENSA. For data dependency cases, I do some jobs in the
adjust_cost target hook.
static int
target_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
{
......
switch (get_attr_type(insn) ){
case TYPE_ARITH_LOGIC:
if (REG_NOTE_KIND (link) == 0 && get_attr_type (dep) == TYPE_LOAD)
return 2;
break;
case TYPE_JUMP_CALL_STORE:
if (REG_NOTE_KIND (link) == 0 && get_attr_type (dep) == TYPE_LOAD)
return 3;
break;
......
}
return 1;
}
When I finished the scheduler, I got a strange phenomenon:
The CPI is reduced, but the total execution cycles are dramatically increased.
I read THE GNU INSTRUCTION SCHEDULER written by Michael D. Tiemann,
which mentioned a similar situation in sparc arch( chapter 7 extension
and future work), This article infromed me that register pressure is a
really big problem during instruction scheduling. I know I must ignore
something critical, but I don't know what it is. Is anyone there
helping me? Thank in advance.
Xiao
