Hello, I used the spim5 gcc 4.0.2 to study gcc port. but I found there are lots of the 'move' insns redundancy code. For example, the C code like this: i=1; i = i + 5; the Spim compiler will generate the code like the following(PS:RX is the register) . li R0, #1 SW R0, 0(MEM) LW R0, 0(MEM) Addi R0, R0, #5 SW R0, 0(MEM)
Obviously, there are two insn redundancy. What confused me is how it generated. Is problem in the 'define_insn mov' pattern or the define_peephole insn? spim5 porting backend code here:http://www.cse.iitb.ac.in/~uday/gcc-workshop/downloads/IITB-Incremental-Machine-Descriptions/ Thank you. Tian Xiaonan ___________________________________________________________ 好玩贺卡等你发，邮箱贺卡全新上线！ http://card.mail.cn.yahoo.com/
