Alan Lehotsky wrote:
Look at the implementation of the IP2K compiler and linker.
It uses a segmented paged architecture just like the machine you are
describing.
In essence what we did was implement linker relaxation to deal with this.
When we called any function, we emitted the appropriate long-call by
setting
the page register and jumping to the location on that page.
In the linker, we implemented relaxation code that looked to see if
we were changing to the SAME page, and if so deleted the instruction
changing
the PAGE and did a local jump to the destination. Now, because a
function could cross a page
boundary (we only had 4kb pages (and 16 bit instructions), all our
branches were done this way
(if I recall correctly).
Yes, every call and branch was emitted in its long form and then relaxed
back down to the shorter form wherever it was possible. A later version
that we had in-house did an even longer sequence that allowed us to
bounce through an emulator to utilize the holes that the architecture
allowed but that weren't physically present on the chip and we'd relax
to either a page-crossing operation or a in-page operation.
Regards,
Dave
