Naveen H.S. wrote:
Hi,
H8SX target supports generation of bit instructions in memory addressing
mode. However, these instructions are not getting generated and the bits
in
memory are operated using other instructions which consume more memory.
The
attached patch "h8sx.patch" generates these bit instructions and hence
generates optimized code.
We are aware that currently GCC is in stage-3. However, this patch is
just
for review so that it can be modified according to the review comments.
The
modified patch will then be posted to the gcc-patches mailing list once
it
returns to stage-1.
Don't forget to include the ChangeLog.
Most of the patch looks OK for when we return to stage1 -- the only
hunks I don't understand are the two peepholes. I'm having trouble
seeing how they can possibly be right. It appears like the peepholes
reverse the order of the branch and bit operation, thus causing the
branch to be based on the output of the bit op rather than whatever was
in cc0 from some previous operation. Can you explain why those two
peepholes are correct, as written?
Additionally, we'd prefer to use define_peephole2 rather than
define_peephole whenever possible, if you could make that change as well
it would be greatly appreciated.
Jeff
