David Daney wrote:
On Wed, Sep 3, 2008 at 6:09 PM, David Edelsohn <[EMAIL PROTECTED]> wrote:
On Wed, Sep 3, 2008 at 6:53 PM, Anton Blanchard <[EMAIL PROTECTED]> wrote:
The only thing lwsync wont order is a store followed by a load. Since
the lwsync will always be paired with a store (the stwcx), we will order
all accesses before it and provide a release barrier.
Anton,
My one other concern is developers using the builtins for applications on
embedded PowerPC processors. lwsync will not order accesses to device
memory space, AFAICT. I do not know if developers would rely on GCC builtins
in that context and assume it implements the correct semantics. Otherwise,
I agree that the memory barrier operations probably can use lwsync.
Would it be possible to have a conservative default and use a more
optimal form based on a specific CPU specified by -mcpu=?
I was thinking of doing something similar on MIPS where there are
similar issues.
Another related issue is that psim in gdb does not currently
support the lwsync instruction so any code generated using it
would fail there. Since this is used as the test platform for
the embedded gcc targets (at least powerpc-elf and powerpc-rtems)
if gcc is going to generate this instruction, the simulator
needs to support it or there will be lots of failures.
David Daney
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