On Tuesday 15 January 2008, Balaji V. Iyer wrote: > Hello Everyone, > I am currently working on dividing the register file into two > different processing element. In the first processing element (PE) I > want to have certain operations (add, sub, mult, div, branch, > jumps..etc) in first PE and loads and stores should be in the 2nd > Processing Element.
Sounds very similar to how many FP coprocessors work. You may also want to look at m68k which has address and data registers. > Now, my question is this: How can I make the register allocator > allocate correctly based on the restrictions I have set? Should just work. See the "Register Classes" section of the internals manual. In particular you may need to define PREFERRED_RELOAD_CLASSand TARGET_SECONDARY_RELOAD. > Secondly, let's say I want to go through the instruction list > (mostly in the machine_dependent_reorg function) and want certain ADDs > to be put in a specific PE. This is mainly done to reduce the number of > inter-PE copies. Is there a way I can set a certain flag (or create a > certain FLAG) on the instruction (I know instruction is an RTX > structure) so that the register allocator can recognize this? You shouldn't need to do this at all, gcc will do it for you. m_d_reorg would be too late anyway. Give your addsi3 pattern alternatives for the different register classes and gcc will pick whichever is best. Constraint modifiers and MOVE_COST allow you to influence the register allocation heuristics. Paul
