"Rohit Arul Raj" <[EMAIL PROTECTED]> writes: > I am adding floating point support to GCC 4.1.1 for a private target. > > My machine can issue > (1) Two instructions, [one integer insns (16 bit) + one floating point > insn (16 bit) ]or > (2) one 32 bit integer insn. > > For case (1) , Since both instructions are executed parallely, there > is no dependecy check between them. > > for e.g. if the generated insn is > mov 5, A0 > movf A0, F0 > > Since both these instructions are executed parallely, the value of F0 > is not 5 but it takes the previous value of A0. > > 1. Is there a way to check for dependency b/w this two instructions. > 2. Any existing backend that has this type of design.
gcc currently does a relatively crummy job of handling this type of VLIW architecture. You can describe the dependencies in the scheduler, but the scheduler won't insert any required nops for you. The usual approach is walk through the insn chain in the MD reorg pass and insert nops at that time. For example, look at mips_reorg in config/mips/mips.c. I've also done it in FINAL_PRESCAN_INSN. Ian
