On Fri, 2006-12-22 at 12:30 -0500, Robert Dewar wrote: > > > Maybe on x86, but on PPC, at least for the (current) Cell's PPU > > misaligned accesses for most cases unaligned are optimal. > > is that true across cache boundaries?
For Cell, crossing the 32byte boundary causes the microcode to happen. But the question is how often does that happen compare to non crossing, I am willing to bet hardly at all, yes I need to test this and I am going to have anyways for my job :). -- Pinski
