> > Two part question: > > 1) Does the control flow graph exist at the time we're emitting assembler > instructions? > > 2) If so, how do I go at getting at the basic block info, specifically > successor info, if the only thing I have is a rtx for a conditional jump > insn? > > > Okay, maybe a 3-part question. Given said jump insn handle, I'm trying to > find out if either of the targets is a loop exit. Is there an easier way > to do so than finding the successor arcs and seeing if either is flagged as > a loop exit?
Higher level reasoning for above questions. I'm looking for an alternate approach to the branch probability problem I encountered. Approach I'm considering is to recognize when a branch is a loop exit and prohibit appending any PowerPC branch hints. -Pat
