hi,
I'm trying to learn mips backend by making some changes to it.I
just tried to decrease the number of general purpose registers to 25
but following error was generated.
dp-bit.c: In function '__muldf3':
dp-bit.c:953: error: insn does not satisfy its constraints:
(insn 677 231 616 19 dp-bit.c:871 (set (reg/v:DI 24 $24 [orig:55 res2 ] [55])
(reg:DI 2 $2)) 3 {*movdi_32bit} (nil)
(nil))
dp-bit.c:953: internal compiler error: in
reload_cse_simplify_operands, at postreload.c:394
I'm compiling the code by setting -msoft-float option and no floating
point register is being used.
Following are the changes made to mips backend
/*25 general purpose ,2 accumulator, 3 fake ,3 dummy entries *\
#define FIRST_PSEUDO_REGISTER 33
#define FIXED_REGISTERS \
{ \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, \
}
#define CALL_USED_REGISTERS \
{ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
0, \
}
#define GP_REG_FIRST 0
#define GP_REG_LAST 24
#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
#define GP_DBX_FIRST 0
#define MD_REG_FIRST 26
#define MD_REG_LAST 27
#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
#define MD_DBX_FIRST 25
#define AT_REGNUM (GP_REG_FIRST + 1)
#define HI_REGNUM (MD_REG_FIRST + 0)
#define LO_REGNUM (MD_REG_FIRST + 1)
enum reg_class
{
NO_REGS, /* no registers in set */
PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
V1_REG, /* Register $v1 ($3) used for TLS access. */
LEA_REGS, /* Every GPR except $25 */
GR_REGS, /* integer registers */
HI_REG, /* hi register */
LO_REG, /* lo register */
MD_REGS, /* multiply/divide registers (hi/lo) */
HI_AND_GR_REGS, /* union classes */
LO_AND_GR_REGS,
ALL_REGS, /* all registers */
LIM_REG_CLASSES /* max value + 1 */
};
#define REG_CLASS_CONTENTS
\
{
\
{ 0x00000000, 0x00000000, }, /* no registers */ \
{ 0x00040000, 0x00000000, }, /* SVR4 PIC function address register $18*/ \
{ 0x00000008, 0x00000000, }, /* only $v1 */ \
{ 0x01bfffff, 0x00000000, }, /* Every other GPR except $18 */ \
{ 0x01ffffff, 0x00000000, }, /* integer registers */ \
{ 0x04000000, 0x00000000, }, /* hi register */ \
{ 0x08000000, 0x00000000, }, /* lo register */ \
{ 0x0c000000, 0x00000000, }, /* mul/div registers */ \
{ 0x05ffffff, 0x00000000, }, /* union classes */ \
{ 0x09ffffff, 0x00000000, }, \
{ 0xffffffff, 0x00000001, } /* all registers */ \
}
#define REGISTER_NAMES \
{ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
"$16", "$17", "$18", "$19", "$20", "$21", "$sp", "$fp", \
"$24", "", "hi", "lo", "$arg", "$frame", "", "", \
"", \
}
#define ADDITIONAL_REGISTER_NAMES \
{ \
{ "$22", 22 + GP_REG_FIRST }, \
{ "$23", 23 + GP_REG_FIRST }, \
{ "at", 1 + GP_REG_FIRST }, \
{ "v0", 2 + GP_REG_FIRST }, \
{ "v1", 3 + GP_REG_FIRST }, \
{ "a0", 4 + GP_REG_FIRST }, \
{ "a1", 5 + GP_REG_FIRST }, \
{ "a2", 6 + GP_REG_FIRST }, \
{ "a3", 7 + GP_REG_FIRST }, \
{ "t0", 8 + GP_REG_FIRST }, \
{ "t1", 9 + GP_REG_FIRST }, \
{ "t2", 10 + GP_REG_FIRST }, \
{ "t3", 11 + GP_REG_FIRST }, \
{ "t4", 12 + GP_REG_FIRST }, \
{ "t5", 13 + GP_REG_FIRST }, \
{ "t6", 14 + GP_REG_FIRST }, \
{ "t7", 15 + GP_REG_FIRST }, \
{ "s0", 16 + GP_REG_FIRST }, \
{ "s1", 17 + GP_REG_FIRST }, \
{ "s2", 18 + GP_REG_FIRST }, \
{ "s3", 19 + GP_REG_FIRST }, \
{ "s4", 20 + GP_REG_FIRST }, \
{ "gp", 21 + GP_REG_FIRST }, \
{ "sp", 22 + GP_REG_FIRST }, \
{ "fp", 23 + GP_REG_FIRST }, \
{ "ra", 24 + GP_REG_FIRST }, \
ALL_COP_ADDITIONAL_REGISTER_NAMES \
}
/* Register to use for pushing function arguments. */
#define STACK_POINTER_REGNUM (GP_REG_FIRST + 22)
/* These two registers don't really exist: they get eliminated to either
the stack or hard frame pointer. */
#define ARG_POINTER_REGNUM 28
#define FRAME_POINTER_REGNUM 29
/* $30 is not available on the mips16, so we use $17 as the frame
pointer. */
#define HARD_FRAME_POINTER_REGNUM GP_REG_FIRST + 23
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, GP_REG_FIRST + 23}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, GP_REG_FIRST + 23}} \
In mips.c file following changes are made
const enum reg_class mips_regno_to_class[] =
{
LEA_REGS, LEA_REGS, LEA_REGS, V1_REG,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, PIC_FN_ADDR_REG, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
LEA_REGS, HI_REG, LO_REG, ALL_REGS,
ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS,
ALL_REGS,
};
and replaced the $31 with $24.
Would you please tell me what might be the cause of error.When i
comment out FLO_type
multiply (FLO_type arg_a, FLO_type arg_b) function in dp-bit.c file
,everything compiles successfully.
thanks,
shaz
