> -----Original Message-----
> From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of
> Rask Ingemann Lambertsen
> Sent: Monday, June 26, 2006 19:25
> To: Roland Persson
> Cc: gcc@gcc.gnu.org
> Subject: Re: Matching of non-standard instructions
>
>
> In a similiar case, only with 8 and 16 bits, respectively, I'm having
> success with this pattern, which you could use as a starting point:
>
> (define_insn "*zero_extendqihi_addhi3"
> [(set (match_operand:HI 0 "nonimmediate_operand" "=q,m")
> (plus:HI (zero_extend:HI (match_operand:QI 1 "general_operand"
> "qmi,qi"))
> (match_operand:HI 2 "nonimmediate_operand" "0,0")))
> (clobber (reg:CC CC_REG))]
> ""
> ...
> )
>
> (It would have been a help to us to see examples of insn patterns you have
> tried unsuccessfully.)
>
>
I've been trying patterns like this one:
(define_insn "*pip_add_di_sesi"
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "register_operand" "r")
(sign_extend:DI (match_operand:SI "register_operand"
"r"))))]
...
)
> In addition to the instruction pattern, you may have to adjust the RTX
> cost calculation (TARGET_RTX_COSTS) so that the optimizers know if this
> instruction is cheaper than two individual instructions. This is not
> difficult as such, but can be a lot of work if you want to do this for all
> instruction patterns and get reasonably accurate costs.
>
I haven't looked at this, so I guess it will be my next step.
Thanks for the help!
Roland
