Ian Lance Taylor wrote:
> Andrew MacLeod <[EMAIL PROTECTED]> writes:
> 
>> This describes my current work-in-progress, RABLET, which stands for
>> RABLE-Themes, and conveniently implies something smaller.
> 
> Thanks for this proposal.
> 
> 
>> ssa-to-rtl
>> spill cost analysis
>> global allocation
>> spiller
>> spill location optimizer
>> instruction rewriter.
> 
> You omitted the RTL loop optimizer passes, which still do quite a bit
> of work despite the tree-ssa loop passes.  Also if-conversion and some
> minor passes, though they are less relevant.
> 
> 
>> If expand is made much smarter, I would argue that much of GCSE and CSE
>> isn't needed.  We've already performed those optimizations at  a high
>> level, and we can hopefully do a lot of the factoring and things on
>> addressing registers exposed during expand.  I'm sure there are other
>> things to do, but I would argue that they are significantly less than a
>> "general purpose" CSE and GCSE pass. And in the cases of high register
>> pressure, how much would you want them to do anyway?  Its really these
>> high register pressure areas that RABLET is attacking anyway.
> 
> Here I think you are waving your hands a little too hard.  RTL level
> CSE is significant for handling common expressions exposed by address
> calculations and by DImode (and larger) computations.  On some
> processors giving up CSE on address calculations would be very
> painful.  There needs to be a plan to handle that.

I agree with Ian completely.
Also, after having stared and worked on df in the backend with Kenny and
watched the amount of work that has had to be done, i think you may be
underestimating the complexity of what is really going on in the backend
right now.

Not that i wouldn't love to see our backend become simpler and have a
bunch of relatively non-complex df based passes, because I would, but i
*also* don't think RABLET is going to enable that (or the removal of
CSE/GCSE) through smarter expand.  It's possible you'd remove GCSE, but
only because the last time i remember someone looking (stevenb, i
think), it wasn't doing all *that* much.

Again, like Ian, I'd argue you'd need to do real instruction selection
before register allocation before that can happen.  Luckily, these days,
BURG based instruction selection has become production usable, so that
task isn't as horrid as it used to be.

--Dan

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