On Sun, 2005-11-13 at 21:20 +0100, Steven Bosscher wrote: > Hi, > > I'm trying to figure out how much effort it would take to make > dbr_schedule CFG aware. One of the issues I'm running into is > that the RTL CFG stuff doesn't support SEQUENCEs at all. So if > I have a delay slot filled, e.g., > > (sequence [ > (jump_insn (...)) ;; The branch with delay slots > (insn (...)) ;; An insn in a delay slot > ]) > > verify_flow_info immediately dies on this because the last insn > in a basic block is not a branch instruction. It sees just the > sequence and not the instructions in it. > > Now I could add some kind of flag "reorg_completed" and go hack > all the RTL cfg routines to support SEQUENCEs. But I'd rather > not do that unless I'm really sure nobody thinks that is a Very > Bad Idea. ;-) No great insights on how to make dbr_schedule CFG aware -- just remember that a filled delay slot can represent 3 different cases:
1. An extension of the block containing the sequence. 2. An extension of the block at the target of a branch. 3. An extension of the fall-thru block. 4. An entirely new basic block on its own. Firing out which of these cases holds can be nontrivial. I'm not sure what you're trying to accomplish, but if you're really interested in improving reorg, a huge step in the right direction would be to have it use insn dependency information to determine what insns are candidates for filling delay slots. The net result is all the resource tracking nonsense goes away as do the compile-time issues associated with it. Jeff
