* Attila Szegedi via Gcc: > We noticed that this version of GCC compiling on aarch64 will happily use > FP registers to temporarily store/load pointers, so there'd be "fmov d9, > x1" to store a pointer, and then later when it's used as a parameter to a > function call we'll see "fmov x1, d9" etc. We noticed this while > investigating some crashes that seemed to always occur in functions called > with parameters loaded through this mechanism, on certain specific models > of aarch64 CPUs. On the face of it, this doesn't seem a _too_ terrible idea > – one'd think that a FP register should preserve the bit pattern so as long > as the only operations are stores and loads, what's the harm, right? Hey, > more free registers! Except, on some silicon, it's unfortunately strongly > correlated with crashes further down the callee chain.
Surely not preserving floating point bit patterns in registers would be a silicon bug? That seems … quite unlikely. GCC 8 has seen extensive use on AArch64, on a variety of implementations, and I don't recall problems in this area. I don't follow AArch64 *that* closely, admittedly, but I expect it would have caused quite a ruckus. Do you use some sort of conservative garbage collector that incorrectly skips scanning of floating point registers?
