The finite automaton used in the pipeline hazard recognizer uses a cycle advancing arc in every state to represent a clock pulse. Bala(1) uses a different technique: All states were a instruction issue is not possible are marked as "cycle advancing" and the pipeline state is update to reflect a clock cycle. Every time the simulation gets to a cycle advancing state, it knows that it cannot issue another instruction in this cycle.
It appears to me that adding a cycle advance arc to every state has the potential of increasing the size of the automaton quite significantly. Is this true? What is the advantage of the "cycle advancing arc"? It is simpler to understand, but the only use I can see is to represent a case were it was possible to issue a instruction but, instead of doing this, the pipeline advanced the clock. Does this happens in practice? 1) V.Bala and N.Rubin, Efficient Instruction Scheduling Using Finite State Automata. Thank you very much. Rafael Ávila de Espíndola
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