On Sat, Mar 19, 2005 at 01:51:05PM -0500, Paul Schlie wrote: > - Fully agree, just can't keep from wondering if this may be most > efficiency accomplish by simply requiring the alignment of all > function entry points to be two instruction word aligned. Thereby
This only doubles the available address space, and I'd rather not do it all again (this time with 4-word alignment) if 512K chips appear. Supporting the maximum possible address space on the AVR would require 64-word function alignment, and shifting the word address by 6. But function entry points are not the only problem - indirect jumps are another (as you can see in the subject of my message), they can point somewhere within a function (so function alignment may not help here). On the other hand, indirect_jump is rarely seen, so it must be correct but doesn't have to be very efficient (OK if it costs even a few more instructions to stay in the low 64K words). So, I'm trying to figure out when the indirect_jump pattern can actually be generated on the AVR (haven't yet seen it in any real application), and where does the pointer comes from (to see if the jump target can be moved to the low 64K words somehow). Marek
