I've now committed all three of these patches, as r/218958 r/218960 and
r/218961, after investigating the effect of the first two on a range of
benchmarks (Spec2000, Geekbench, Spec2k6) and finding almost no effect on
codegen and no significant performance difference on Cortex-A53 or Cortex-A57.
Cheers, Alan
On Tue, 12 Aug 2014 15:38:09, Alan Lawrence <alan.lawre...@arm.com> wrote:
Following the change to make arm_neon.h's (u?)int64x1_t types into vectors,
these types are now passed in the SIMD registers rather than general purpose
registers, which often results in poor quality code in functions taking or
returning these types. Often values are moved from vector registers into GPRs,
an operation performed, and the value moved back - yet the architecture is
capable of performing the operation directly on the SIMD registers. Hence these
patches are small tweaks to the relevant patterns.
The third patch, allowing AND+OR directly on values in SIMD registers, is more
complicated, as the XOR pattern there was never matched (due to action of
simplify_rtx) - the new pattern should also start to be used in GPR registers.
Regression-tested check-gcc check-g++ on aarch64-none-elf and
aarch64_be-none-elf.
