This patch is discussed in PR55212
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c65
and is to make LRA's register elimination work well on SH.
The problem is SH has very limited add instructions only and expands
rA := rB + N to (set rA (const_int N)) and (set rA (plus rA rB))
instead of (set rA (plus rB (const_int N))). It seems that the former
combination isn't good for LRA's register elimination pass. The patch
adds splitter to addsi3_compact insn so that LRA can see the latter
rtl.
--
* config/sh/predicates.md (arith_or_int_operand): New predicate.
* config/sh/sh.md (addsi3): Use arith_or_int_operand for operand 2.
Return fail if operands[0] and operands[1] are overlap when
operands[2] is integer constant.
(*addsi3_compact): Make it define_insn_and_split which splits
reg0 := reg1 + constant to reg0 = constant and reg0 := reg0 + reg1.
diff --git a/config/sh/predicates.md b/config/sh/predicates.md
index 152056a..8772332 100644
--- a/config/sh/predicates.md
+++ b/config/sh/predicates.md
@@ -182,6 +182,19 @@
return 0;
})
+;; Likewise arith_operand but always permits const_int.
+(define_predicate "arith_or_int_operand"
+ (match_code "subreg,reg,const_int,const_vector")
+{
+ if (arith_operand (op, mode))
+ return 1;
+
+ if (CONST_INT_P (op))
+ return 1;
+
+ return 0;
+})
+
;; Returns 1 if OP is a valid source operand for a compare insn.
(define_predicate "arith_reg_or_0_operand"
(match_code "subreg,reg,const_int,const_vector")
diff --git a/config/sh/sh.md b/config/sh/sh.md
index 6bc0084..bcc569d 100644
--- a/config/sh/sh.md
+++ b/config/sh/sh.md
@@ -2061,11 +2061,16 @@
(define_expand "addsi3"
[(set (match_operand:SI 0 "arith_reg_operand" "")
(plus:SI (match_operand:SI 1 "arith_operand" "")
- (match_operand:SI 2 "arith_operand" "")))]
+ (match_operand:SI 2 "arith_or_int_operand" "")))]
""
{
if (TARGET_SHMEDIA)
operands[1] = force_reg (SImode, operands[1]);
+ else if (! arith_operand (operands[2], SImode))
+ {
+ if (reg_overlap_mentioned_p (operands[0], operands[1]))
+ FAIL;
+ }
})
(define_insn "addsi3_media"
@@ -2092,12 +2097,22 @@
[(set_attr "type" "arith_media")
(set_attr "highpart" "ignore")])
-(define_insn "*addsi3_compact"
- [(set (match_operand:SI 0 "arith_reg_dest" "=r")
- (plus:SI (match_operand:SI 1 "arith_operand" "%0")
- (match_operand:SI 2 "arith_operand" "rI08")))]
- "TARGET_SH1"
- "add %2,%0"
+(define_insn_and_split "*addsi3_compact"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=r,&r")
+ (plus:SI (match_operand:SI 1 "arith_operand" "%0,r")
+ (match_operand:SI 2 "arith_or_int_operand" "rI08,rn")))]
+ "TARGET_SH1
+ && (rtx_equal_p (operands[0], operands[1])
+ && arith_operand (operands[2], SImode))
+ || ! reg_overlap_mentioned_p (operands[0], operands[1])"
+ "@
+ add %2,%0
+ #"
+ "reload_completed
+ && ! reg_overlap_mentioned_p (operands[0], operands[1])"
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
+ ""
[(set_attr "type" "arith")])
;; -------------------------------------------------------------------------
