Hi, New revision of Intel ISA reference [1] has new instructions: Clwb, pcommit and new flavors of AVX512. Patch bellow adds them. I understand that stage 1 is closed, however those changes shouldn't affect anything outside if i386 backend. And are extremely unlikely to break existing functionality, and I personally think it's desirable for newest GCC to support newest spec. Bootstrapped/regtestsed on x86_64-unknown-linux-gnu. Ok for trunk?
[1]:https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf gcc/ 2014-11-19 Ilya Tocar <ilya.to...@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512IFMA_SET, OPTION_MASK_ISA_AVX512VBMI_SET, OPTION_MASK_ISA_AVX512IFMA_UNSET, OPTION_MASK_ISA_AVX512VBMI_UNSET, OPTION_MASK_ISA_PCOMMIT_UNSET, OPTION_MASK_ISA_CLWB_UNSET, OPTION_MASK_ISA_CLWB_SET, OPTION_MASK_ISA_PCOMMIT_SET): New. (ix86_handle_option): Handle OPT_mavx512ifma, OPT_mavx512vbmi, OPT_mpcommit, OPT_mclwb. * config.gcc: Add avx512ifmaintrin.h, avx512ifmavlintrin.h, avx512vbmiintrin.h, avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h * config/i386/avx512ifmaintrin.h: New file. * config/i386/avx512ifmaivlntrin.h: Ditto. * config/i386/avx512vbmiintrin.h: Ditto. * config/i386/avx512vbmivlintrin.h: Ditto. * config/i386/clwbintrin.h: Ditto. * config/i386/pcommitintrin.h: Ditto. * config/i386/cpuid.h (bit_AVX512IFMA, bit_PCOMMIT, bit_CLWB, bit_AVX512VBMI): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect pcommit, clwb, avx512ifma, avx512vbmi. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX512VBMI__, __AVX512IFMA__, __PCOMMIT__, __CLWB__. * config/i386/i386.c (ix86_target_string): Add -mavx512ifma, -mavx512vbmi, -mclwb, -mpcommit. (PTA_AVX512VBMI, PTA_AVX512IFMA, PTA_CLWB, PTA_PCOMMIT): Define. (ix86_option_override_internal): Handle new options. (ix86_valid_target_attribute_inner_p): Add avx512vbmi, avx512ifma, clwb, pcommit. (ix86_builtins): Add IX86_BUILTIN_VPMADD52LUQ512, IX86_BUILTIN_VPMADD52HUQ512, IX86_BUILTIN_VPMADD52LUQ256, IX86_BUILTIN_VPMADD52HUQ256, IX86_BUILTIN_VPMADD52LUQ128, IX86_BUILTIN_VPMADD52HUQ128, IX86_BUILTIN_VPMADD52LUQ512_MASKZ, IX86_BUILTIN_VPMADD52HUQ512_MASKZ, IX86_BUILTIN_VPMADD52LUQ256_MASKZ, IX86_BUILTIN_VPMADD52HUQ256_MASKZ, IX86_BUILTIN_VPMADD52LUQ128_MASKZ, IX86_BUILTIN_VPMADD52HUQ128_MASKZ, IX86_BUILTIN_VPMULTISHIFTQB512, IX86_BUILTIN_VPMULTISHIFTQB256, IX86_BUILTIN_VPMULTISHIFTQB128, IX86_BUILTIN_VPERMVARQI512_MASK, IX86_BUILTIN_VPERMT2VARQI512, IX86_BUILTIN_VPERMT2VARQI512_MASKZ, IX86_BUILTIN_VPERMI2VARQI512, IX86_BUILTIN_VPERMVARQI256_MASK, IX86_BUILTIN_VPERMVARQI128_MASK, IX86_BUILTIN_VPERMT2VARQI256, IX86_BUILTIN_VPERMT2VARQI256_MASKZ, IX86_BUILTIN_VPERMT2VARQI128, IX86_BUILTIN_VPERMI2VARQI256, IX86_BUILTIN_VPERMI2VARQI128, IX86_BUILTIN_CLWB, IX86_BUILTIN_PCOMMIT. (bdesc_special_args): Add __builtin_ia32_pcommit, __builtin_ia32_vpmadd52luq512_mask, __builtin_ia32_vpmadd52luq512_maskz, __builtin_ia32_vpmadd52huq512_mask, __builtin_ia32_vpmadd52huq512_maskx, __builtin_ia32_vpmadd52luq256_mask, __builtin_ia32_vpmadd52luq256_maskz, __builtin_ia32_vpmadd52huq256_mask, __builtin_ia32_vpmadd52huq256_maskz, __builtin_ia32_vpmadd52luq128_mask, __builtin_ia32_vpmadd52luq128_maskz, __builtin_ia32_vpmadd52huq128_mask, __builtin_ia32_vpmadd52huq128_maskz, __builtin_ia32_vpmultishiftqb512_mask, __builtin_ia32_vpmultishiftqb256_mask, __builtin_ia32_vpmultishiftqb128_mask, __builtin_ia32_permvarqi512_mask, __builtin_ia32_vpermt2varqi512_mask, __builtin_ia32_vpermt2varqi512_maskz, __builtin_ia32_vpermi2varqi512_mask, __builtin_ia32_permvarqi256_mask, __builtin_ia32_permvarqi128_mask, __builtin_ia32_vpermt2varqi256_mask, __builtin_ia32_vpermt2varqi256_maskz, __builtin_ia32_vpermt2varqi128_mask, __builtin_ia32_vpermt2varqi128_maskz, __builtin_ia32_vpermi2varqi256_mask, __builtin_ia32_vpermi2varqi128_mask. (ix86_init_mmx_sse_builtins): Add __builtin_ia32_clwb. (ix86_expand_builtin): Handle IX86_BUILTIN_CLWB. (ix86_hard_regno_mode_ok): Allow big masks for AVX612VBMI. * config/i386/i386.h (TARGET_AVX512VBMI, TARGET_AVX512VBMI_P, TARGET_AVX512IFMA, TARGET_AVX512IFMA_P, TARGET_PCOMMIT, TARGET_PCOMMIT_P, TARGET_CLWB, TARGET_CLWB_P): Define. * config/i386/i386.md (unspecv): Add UNSPECV_CLWB, UNSPECV_PCOMMIT. (pcommit): New instruction. (clwb): Ditto. * config/i386/i386.opt: Add mavx512ifma, mavx512vbmi, mclwb, mpcommit. * config/i386/immintrin.h: Include avx512ifmaintrin.h, avx512ifmavlintrin.h, avx512vbmiintrin.h, avx512vbmivlintrin.h. * config/i386/sse.md (unspec): Add UNSPEC_VPMADD52LUQ, UNSPEC_VPMADD52HUQ, UNSPEC_VPMULTISHIFT. (VI1_AVX512VL): New iterator. (<avx512>_permvar<mode><mask_name>): Use it. (<avx512>_vpermi2var<mode>3_maskz): Ditto. (<avx512>_vpermi2var<mode>3<sd_maskz_name>): Ditto. (<avx512>_vpermi2var<mode>3_mask): Ditto. (<avx512>_vpermt2var<mode>3_maskz): Ditto. (<avx512>_vpermt2var<mode>3<sd_maskz_name>): Ditto. (<avx512>_vpermt2var<mode>3_mask): Ditto. (VPMADD52): New iterator. (vpmadd52type): New attribute. (vpamdd52huq<mode>_maskz): New. (vpamdd52luq<mode>_maskz): Ditto. (vpamdd52<vpmadd52type><mode><sd_maskz_name>): Ditto. (vpamdd52<vpmadd52type><mode>_mask): Ditto. (vpmultishiftqb<mode><mask_name>): Ditto. * config/i386/x86intrin.h: Include clwbintrin.h, pcommitintrin.h. gcc/testsuite/ 2014-11-19 Ilya Tocar <ilya.to...@intel.com> * g++.dg/other/i386-2.C: Add -mavx512ifma -mavx512vbmi -mclwb -mpcommit. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx512f-helper.h: Add avx512ifma-check.h, avx512vbmi-check.h. * gcc.target/i386/avx512ifma-check.h: New. * gcc.target/i386/avx512ifma-vpmaddhuq-1.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddhuq-2.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddluq-1.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddluq-2.c: Ditto. * gcc.target/i386/avx512vbmi-check.h: Ditto. * gcc.target/i386/avx512vbmi-vpermb-1.c: Ditto. * gcc.target/i386/avx512vbmi-vpermb-2.c: Ditto. * gcc.target/i386/avx512vbmi-vpermi2b-1.c: Ditto. * gcc.target/i386/avx512vbmi-vpermi2b-2.c: Ditto. * gcc.target/i386/avx512vbmi-vpermt2b-1.c: Ditto. * gcc.target/i386/avx512vbmi-vpermt2b-2.c: Ditto. * gcc.target/i386/avx512vbmi-vpmultishiftqb-1.c: Ditto. * gcc.target/i386/avx512vbmi-vpmultishiftqb-2.c: Ditto. * gcc.target/i386/avx512vl-vpermb-2.c: Ditto. * gcc.target/i386/avx512vl-vpermi2b-2.c: Ditto. * gcc.target/i386/avx512vl-vpermt2b-2.c: Ditto. * gcc.target/i386/avx512vl-vpmaddhuq-2.c: Ditto. * gcc.target/i386/avx512vl-vpmaddluq-2.c: Ditto. * gcc.target/i386/avx512vl-vpmultishiftqb-2.c: Ditto. * gcc.target/i386/clwb-1.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_avx512ifma, check_effective_target_avx512vbmi): New. * gcc.target/i386/pcommit-1.c: Ditto. * gcc.target/i386/sse-12.c: Add new options. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. --- gcc/common/config/i386/i386-common.c | 62 +++++ gcc/config.gcc | 8 +- gcc/config/i386/avx512ifmaintrin.h | 104 ++++++++ gcc/config/i386/avx512ifmavlintrin.h | 164 ++++++++++++ gcc/config/i386/avx512vbmiintrin.h | 159 ++++++++++++ gcc/config/i386/avx512vbmivlintrin.h | 275 +++++++++++++++++++++ gcc/config/i386/clwbintrin.h | 49 ++++ gcc/config/i386/cpuid.h | 4 + gcc/config/i386/driver-i386.c | 12 +- gcc/config/i386/i386-c.c | 8 + gcc/config/i386/i386.c | 112 ++++++++- gcc/config/i386/i386.h | 8 + gcc/config/i386/i386.md | 22 ++ gcc/config/i386/i386.opt | 16 ++ gcc/config/i386/immintrin.h | 8 + gcc/config/i386/pcommitintrin.h | 49 ++++ gcc/config/i386/sse.md | 184 ++++++++++++++ gcc/config/i386/x86intrin.h | 4 + gcc/testsuite/g++.dg/other/i386-2.C | 2 +- gcc/testsuite/g++.dg/other/i386-3.C | 2 +- gcc/testsuite/gcc.target/i386/avx512f-helper.h | 10 + gcc/testsuite/gcc.target/i386/avx512ifma-check.h | 46 ++++ .../gcc.target/i386/avx512ifma-vpmaddhuq-1.c | 31 +++ .../gcc.target/i386/avx512ifma-vpmaddhuq-2.c | 62 +++++ .../gcc.target/i386/avx512ifma-vpmaddluq-1.c | 31 +++ .../gcc.target/i386/avx512ifma-vpmaddluq-2.c | 53 ++++ gcc/testsuite/gcc.target/i386/avx512vbmi-check.h | 46 ++++ .../gcc.target/i386/avx512vbmi-vpermb-1.c | 34 +++ .../gcc.target/i386/avx512vbmi-vpermb-2.c | 51 ++++ .../gcc.target/i386/avx512vbmi-vpermi2b-1.c | 25 ++ .../gcc.target/i386/avx512vbmi-vpermi2b-2.c | 58 +++++ .../gcc.target/i386/avx512vbmi-vpermt2b-1.c | 37 +++ .../gcc.target/i386/avx512vbmi-vpermt2b-2.c | 70 ++++++ .../gcc.target/i386/avx512vbmi-vpmultishiftqb-1.c | 31 +++ .../gcc.target/i386/avx512vbmi-vpmultishiftqb-2.c | 68 +++++ gcc/testsuite/gcc.target/i386/avx512vl-vpermb-2.c | 14 ++ .../gcc.target/i386/avx512vl-vpermi2b-2.c | 14 ++ .../gcc.target/i386/avx512vl-vpermt2b-2.c | 14 ++ .../gcc.target/i386/avx512vl-vpmaddhuq-2.c | 14 ++ .../gcc.target/i386/avx512vl-vpmaddluq-2.c | 14 ++ .../gcc.target/i386/avx512vl-vpmultishiftqb-2.c | 14 ++ gcc/testsuite/gcc.target/i386/clwb-1.c | 11 + gcc/testsuite/gcc.target/i386/i386.exp | 30 +++ gcc/testsuite/gcc.target/i386/pcommit-1.c | 11 + gcc/testsuite/gcc.target/i386/sse-12.c | 2 +- gcc/testsuite/gcc.target/i386/sse-13.c | 2 +- gcc/testsuite/gcc.target/i386/sse-14.c | 2 +- gcc/testsuite/gcc.target/i386/sse-22.c | 6 +- gcc/testsuite/gcc.target/i386/sse-23.c | 2 +- 49 files changed, 2042 insertions(+), 13 deletions(-) create mode 100644 gcc/config/i386/avx512ifmaintrin.h create mode 100644 gcc/config/i386/avx512ifmavlintrin.h create mode 100644 gcc/config/i386/avx512vbmiintrin.h create mode 100644 gcc/config/i386/avx512vbmivlintrin.h create mode 100644 gcc/config/i386/clwbintrin.h create mode 100644 gcc/config/i386/pcommitintrin.h create mode 100644 gcc/testsuite/gcc.target/i386/avx512ifma-check.h create mode 100644 gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddhuq-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddhuq-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddluq-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddluq-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vbmi-check.h create mode 100644 gcc/testsuite/gcc.target/i386/avx512vbmi-vpermb-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vbmi-vpermb-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vbmi-vpermi2b-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vbmi-vpermi2b-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vbmi-vpermt2b-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vbmi-vpermt2b-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vbmi-vpmultishiftqb-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vbmi-vpmultishiftqb-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpermb-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpermi2b-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpermt2b-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpmaddhuq-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpmaddluq-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpmultishiftqb-2.c create mode 100644 gcc/testsuite/gcc.target/i386/clwb-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pcommit-1.c diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index da47e64..2e09d77 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -71,6 +71,10 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_AVX512VL_SET \ (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512IFMA_SET \ + (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512VBMI_SET \ + (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED @@ -81,6 +85,8 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE) #define OPTION_MASK_ISA_XSAVEC_SET \ (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE) +#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB +#define OPTION_MASK_ISA_PCOMMIT_SET OPTION_MASK_ISA_PCOMMIT /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -167,6 +173,8 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ #define OPTION_MASK_ISA_AVX512BW_UNSET OPTION_MASK_ISA_AVX512BW #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL +#define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA +#define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED @@ -175,6 +183,8 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES +#define OPTION_MASK_ISA_PCOMMIT_UNSET OPTION_MASK_ISA_PCOMMIT +#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -443,6 +453,32 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mavx512ifma: + if (value) + { + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET; + } + else + { + opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET; + } + return true; + + case OPT_mavx512vbmi: + if (value) + { + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET; + } + else + { + opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET; + } + return true; + case OPT_mfma: if (value) { @@ -869,6 +905,32 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mpcommit: + if (value) + { + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCOMMIT_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCOMMIT_SET; + } + else + { + opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCOMMIT_UNSET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCOMMIT_UNSET; + } + return true; + + case OPT_mclwb: + if (value) + { + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET; + } + else + { + opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET; + } + return true; + /* Comes from final.c -- no real reason to change it. */ #define MAX_CODE_ALIGN 16 diff --git a/gcc/config.gcc b/gcc/config.gcc index 88309b6..fa3e1fc 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -367,7 +367,9 @@ i[34567]86-*-*) avx512cdintrin.h avx512erintrin.h avx512pfintrin.h shaintrin.h clflushoptintrin.h xsavecintrin.h xsavesintrin.h avx512dqintrin.h avx512bwintrin.h - avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h" + avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h + avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h + avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h" ;; x86_64-*-*) cpu_type=i386 @@ -386,7 +388,9 @@ x86_64-*-*) avx512cdintrin.h avx512erintrin.h avx512pfintrin.h shaintrin.h clflushoptintrin.h xsavecintrin.h xsavesintrin.h avx512dqintrin.h avx512bwintrin.h - avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h" + avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h + avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h + avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/avx512ifmaintrin.h b/gcc/config/i386/avx512ifmaintrin.h new file mode 100644 index 0000000..45b0829 --- /dev/null +++ b/gcc/config/i386/avx512ifmaintrin.h @@ -0,0 +1,104 @@ +/* Copyright (C) 2013-2014 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _IMMINTRIN_H_INCLUDED +#error "Never use <avx512ifmaintrin.h> directly; include <immintrin.h> instead." +#endif + +#ifndef _AVX512IFMAINTRIN_H_INCLUDED +#define _AVX512IFMAINTRIN_H_INCLUDED + +#ifndef __AVX512IFMA__ +#pragma GCC push_options +#pragma GCC target("avx512ifma") +#define __DISABLE_AVX512IFMA__ +#endif /* __AVX512IFMA__ */ + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_madd52lo_epu64 (__m512i __X, __m512i __Y, __m512i __Z) +{ + return (__m512i) __builtin_ia32_vpmadd52luq512_mask ((__v8di) __X, + (__v8di) __Y, + (__v8di) __Z, + (__mmask8) - 1); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_madd52hi_epu64 (__m512i __X, __m512i __Y, __m512i __Z) +{ + return (__m512i) __builtin_ia32_vpmadd52huq512_mask ((__v8di) __X, + (__v8di) __Y, + (__v8di) __Z, + (__mmask8) - 1); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_madd52lo_epu64 (__m512i __W, __mmask8 __M, __m512i __X, + __m512i __Y) +{ + return (__m512i) __builtin_ia32_vpmadd52luq512_mask ((__v8di) __W, + (__v8di) __X, + (__v8di) __Y, + (__mmask8) __M); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_madd52hi_epu64 (__m512i __W, __mmask8 __M, __m512i __X, + __m512i __Y) +{ + return (__m512i) __builtin_ia32_vpmadd52huq512_mask ((__v8di) __W, + (__v8di) __X, + (__v8di) __Y, + (__mmask8) __M); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_madd52lo_epu64 (__mmask8 __M, __m512i __X, __m512i __Y, __m512i __Z) +{ + return (__m512i) __builtin_ia32_vpmadd52luq512_maskz ((__v8di) __X, + (__v8di) __Y, + (__v8di) __Z, + (__mmask8) __M); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_madd52hi_epu64 (__mmask8 __M, __m512i __X, __m512i __Y, __m512i __Z) +{ + return (__m512i) __builtin_ia32_vpmadd52huq512_maskz ((__v8di) __X, + (__v8di) __Y, + (__v8di) __Z, + (__mmask8) __M); +} + +#ifdef __DISABLE_AVX512IFMA__ +#undef __DISABLE_AVX512IFMA__ +#pragma GCC pop_options +#endif /* __DISABLE_AVX512IFMA__ */ + +#endif /* _AVX512IFMAINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/avx512ifmavlintrin.h b/gcc/config/i386/avx512ifmavlintrin.h new file mode 100644 index 0000000..7c858ba --- /dev/null +++ b/gcc/config/i386/avx512ifmavlintrin.h @@ -0,0 +1,164 @@ +/* Copyright (C) 2013-2014 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _IMMINTRIN_H_INCLUDED +#error "Never use <avx512ifmavlintrin.h> directly; include <immintrin.h> instead." +#endif + +#ifndef _AVX512IFMAVLINTRIN_H_INCLUDED +#define _AVX512IFMAVLINTRIN_H_INCLUDED + +#if !defined(__AVX512VL__) || !defined(__AVX512IFMA__) +#pragma GCC push_options +#pragma GCC target("avx512ifma,avx512vl") +#define __DISABLE_AVX512IFMAVL__ +#endif /* __AVX512IFMAVL__ */ + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_madd52lo_epu64 (__m128i __X, __m128i __Y, __m128i __Z) +{ + return (__m128i) __builtin_ia32_vpmadd52luq128_mask ((__v2di) __X, + (__v2di) __Y, + (__v2di) __Z, + (__mmask8) - 1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_madd52hi_epu64 (__m128i __X, __m128i __Y, __m128i __Z) +{ + return (__m128i) __builtin_ia32_vpmadd52huq128_mask ((__v2di) __X, + (__v2di) __Y, + (__v2di) __Z, + (__mmask8) - 1); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_madd52lo_epu64 (__m256i __X, __m256i __Y, __m256i __Z) +{ + return (__m256i) __builtin_ia32_vpmadd52luq256_mask ((__v4di) __X, + (__v4di) __Y, + (__v4di) __Z, + (__mmask8) - 1); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_madd52hi_epu64 (__m256i __X, __m256i __Y, __m256i __Z) +{ + return (__m256i) __builtin_ia32_vpmadd52huq256_mask ((__v4di) __X, + (__v4di) __Y, + (__v4di) __Z, + (__mmask8) - 1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_madd52lo_epu64 (__m128i __W, __mmask8 __M, __m128i __X, __m128i __Y) +{ + return (__m128i) __builtin_ia32_vpmadd52luq128_mask ((__v2di) __W, + (__v2di) __X, + (__v2di) __Y, + (__mmask8) __M); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_madd52hi_epu64 (__m128i __W, __mmask8 __M, __m128i __X, __m128i __Y) +{ + return (__m128i) __builtin_ia32_vpmadd52huq128_mask ((__v2di) __W, + (__v2di) __X, + (__v2di) __Y, + (__mmask8) __M); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_madd52lo_epu64 (__m256i __W, __mmask8 __M, __m256i __X, + __m256i __Y) +{ + return (__m256i) __builtin_ia32_vpmadd52luq256_mask ((__v4di) __W, + (__v4di) __X, + (__v4di) __Y, + (__mmask8) __M); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_madd52hi_epu64 (__m256i __W, __mmask8 __M, __m256i __X, + __m256i __Y) +{ + return (__m256i) __builtin_ia32_vpmadd52huq256_mask ((__v4di) __W, + (__v4di) __X, + (__v4di) __Y, + (__mmask8) __M); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_madd52lo_epu64 (__mmask8 __M, __m128i __X, __m128i __Y, __m128i __Z) +{ + return (__m128i) __builtin_ia32_vpmadd52luq128_maskz ((__v2di) __X, + (__v2di) __Y, + (__v2di) __Z, + (__mmask8) __M); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_madd52hi_epu64 (__mmask8 __M, __m128i __X, __m128i __Y, __m128i __Z) +{ + return (__m128i) __builtin_ia32_vpmadd52huq128_maskz ((__v2di) __X, + (__v2di) __Y, + (__v2di) __Z, + (__mmask8) __M); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_madd52lo_epu64 (__mmask8 __M, __m256i __X, __m256i __Y, __m256i __Z) +{ + return (__m256i) __builtin_ia32_vpmadd52luq256_maskz ((__v4di) __X, + (__v4di) __Y, + (__v4di) __Z, + (__mmask8) __M); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_madd52hi_epu64 (__mmask8 __M, __m256i __X, __m256i __Y, __m256i __Z) +{ + return (__m256i) __builtin_ia32_vpmadd52huq256_maskz ((__v4di) __X, + (__v4di) __Y, + (__v4di) __Z, + (__mmask8) __M); +} + +#ifdef __DISABLE_AVX512IFMAVL__ +#undef __DISABLE_AVX512IFMAVL__ +#pragma GCC pop_options +#endif /* __DISABLE_AVX512IFMAVL__ */ + +#endif /* _AVX512IFMAVLINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/avx512vbmiintrin.h b/gcc/config/i386/avx512vbmiintrin.h new file mode 100644 index 0000000..c2c59ce --- /dev/null +++ b/gcc/config/i386/avx512vbmiintrin.h @@ -0,0 +1,159 @@ +/* Copyright (C) 2013-2014 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _IMMINTRIN_H_INCLUDED +#error "Never use <avx512vbmiintrin.h> directly; include <immintrin.h> instead." +#endif + +#ifndef _AVX512VBMIINTRIN_H_INCLUDED +#define _AVX512VBMIINTRIN_H_INCLUDED + +#ifndef __AVX512VBMI__ +#pragma GCC push_options +#pragma GCC target("avx512vbmi") +#define __DISABLE_AVX512VBMI__ +#endif /* __AVX512VBMI__ */ + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_multishift_epi64_epi8 (__m512i __W, __mmask64 __M, __m512i __X, __m512i __Y) +{ + return (__m512i) __builtin_ia32_vpmultishiftqb512_mask ((__v64qi) __X, + (__v64qi) __Y, + (__v64qi) __W, + (__mmask64) __M); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_multishift_epi64_epi8 (__mmask64 __M, __m512i __X, __m512i __Y) +{ + return (__m512i) __builtin_ia32_vpmultishiftqb512_mask ((__v64qi) __X, + (__v64qi) __Y, + (__v64qi) + _mm512_setzero_si512 (), + (__mmask64) __M); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_multishift_epi64_epi8 (__m512i __X, __m512i __Y) +{ + return (__m512i) __builtin_ia32_vpmultishiftqb512_mask ((__v64qi) __X, + (__v64qi) __Y, + (__v64qi) + _mm512_undefined_si512 (), + (__mmask64) -1); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_permutexvar_epi8 (__m512i __A, __m512i __B) +{ + return (__m512i) __builtin_ia32_permvarqi512_mask ((__v64qi) __B, + (__v64qi) __A, + (__v64qi) + _mm512_undefined_si512 (), + (__mmask64) -1); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_permutexvar_epi8 (__mmask64 __M, __m512i __A, + __m512i __B) +{ + return (__m512i) __builtin_ia32_permvarqi512_mask ((__v64qi) __B, + (__v64qi) __A, + (__v64qi) + _mm512_setzero_si512(), + (__mmask64) __M); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_permutexvar_epi8 (__m512i __W, __mmask64 __M, __m512i __A, + __m512i __B) +{ + return (__m512i) __builtin_ia32_permvarqi512_mask ((__v64qi) __B, + (__v64qi) __A, + (__v64qi) __W, + (__mmask64) __M); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_permutex2var_epi8 (__m512i __A, __m512i __I, __m512i __B) +{ + return (__m512i) __builtin_ia32_vpermt2varqi512_mask ((__v64qi) __I + /* idx */ , + (__v64qi) __A, + (__v64qi) __B, + (__mmask64) - + 1); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_permutex2var_epi8 (__m512i __A, __mmask64 __U, + __m512i __I, __m512i __B) +{ + return (__m512i) __builtin_ia32_vpermt2varqi512_mask ((__v64qi) __I + /* idx */ , + (__v64qi) __A, + (__v64qi) __B, + (__mmask64) + __U); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask2_permutex2var_epi8 (__m512i __A, __m512i __I, + __mmask64 __U, __m512i __B) +{ + return (__m512i) __builtin_ia32_vpermi2varqi512_mask ((__v64qi) __A, + (__v64qi) __I + /* idx */ , + (__v64qi) __B, + (__mmask64) + __U); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_permutex2var_epi8 (__mmask64 __U, __m512i __A, + __m512i __I, __m512i __B) +{ + return (__m512i) __builtin_ia32_vpermt2varqi512_maskz ((__v64qi) __I + /* idx */ , + (__v64qi) __A, + (__v64qi) __B, + (__mmask64) + __U); +} + +#ifdef __DISABLE_AVX512VBMI__ +#undef __DISABLE_AVX512VBMI__ +#pragma GCC pop_options +#endif /* __DISABLE_AVX512VBMI__ */ + +#endif /* _AVX512VBMIINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/avx512vbmivlintrin.h b/gcc/config/i386/avx512vbmivlintrin.h new file mode 100644 index 0000000..b4ecdeb --- /dev/null +++ b/gcc/config/i386/avx512vbmivlintrin.h @@ -0,0 +1,275 @@ +/* Copyright (C) 2013-2014 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _IMMINTRIN_H_INCLUDED +#error "Never use <avx512vbmivlintrin.h> directly; include <immintrin.h> instead." +#endif + +#ifndef _AVX512VBMIVLINTRIN_H_INCLUDED +#define _AVX512VBMIVLINTRIN_H_INCLUDED + +#if !defined(__AVX512VL__) || !defined(__AVX512VBMI__) +#pragma GCC push_options +#pragma GCC target("avx512vbmi,avx512vl") +#define __DISABLE_AVX512VBMIVL__ +#endif /* __AVX512VBMIVL__ */ + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_multishift_epi64_epi8 (__m256i __W, __mmask32 __M, __m256i __X, __m256i __Y) +{ + return (__m256i) __builtin_ia32_vpmultishiftqb256_mask ((__v32qi) __X, + (__v32qi) __Y, + (__v32qi) __W, + (__mmask32) __M); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_multishift_epi64_epi8 (__mmask32 __M, __m256i __X, __m256i __Y) +{ + return (__m256i) __builtin_ia32_vpmultishiftqb256_mask ((__v32qi) __X, + (__v32qi) __Y, + (__v32qi) + _mm256_setzero_si256 (), + (__mmask32) __M); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_multishift_epi64_epi8 (__m256i __X, __m256i __Y) +{ + return (__m256i) __builtin_ia32_vpmultishiftqb256_mask ((__v32qi) __X, + (__v32qi) __Y, + (__v32qi) + _mm256_undefined_si256 (), + (__mmask32) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_multishift_epi64_epi8 (__m128i __W, __mmask16 __M, __m128i __X, __m128i __Y) +{ + return (__m128i) __builtin_ia32_vpmultishiftqb128_mask ((__v16qi) __X, + (__v16qi) __Y, + (__v16qi) __W, + (__mmask16) __M); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_multishift_epi64_epi8 (__mmask16 __M, __m128i __X, __m128i __Y) +{ + return (__m128i) __builtin_ia32_vpmultishiftqb128_mask ((__v16qi) __X, + (__v16qi) __Y, + (__v16qi) + _mm_setzero_si128 (), + (__mmask16) __M); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_multishift_epi64_epi8 (__m128i __X, __m128i __Y) +{ + return (__m128i) __builtin_ia32_vpmultishiftqb128_mask ((__v16qi) __X, + (__v16qi) __Y, + (__v16qi) + _mm_undefined_si128 (), + (__mmask16) -1); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_permutexvar_epi8 (__m256i __A, __m256i __B) +{ + return (__m256i) __builtin_ia32_permvarqi256_mask ((__v32qi) __B, + (__v32qi) __A, + (__v32qi) + _mm256_undefined_si256 (), + (__mmask32) -1); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_permutexvar_epi8 (__mmask32 __M, __m256i __A, + __m256i __B) +{ + return (__m256i) __builtin_ia32_permvarqi256_mask ((__v32qi) __B, + (__v32qi) __A, + (__v32qi) + _mm256_setzero_si256 (), + (__mmask32) __M); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_permutexvar_epi8 (__m256i __W, __mmask32 __M, __m256i __A, + __m256i __B) +{ + return (__m256i) __builtin_ia32_permvarqi256_mask ((__v32qi) __B, + (__v32qi) __A, + (__v32qi) __W, + (__mmask32) __M); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_permutexvar_epi8 (__m128i __A, __m128i __B) +{ + return (__m128i) __builtin_ia32_permvarqi128_mask ((__v16qi) __B, + (__v16qi) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask16) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_permutexvar_epi8 (__mmask16 __M, __m128i __A, __m128i __B) +{ + return (__m128i) __builtin_ia32_permvarqi128_mask ((__v16qi) __B, + (__v16qi) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask16) __M); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_permutexvar_epi8 (__m128i __W, __mmask16 __M, __m128i __A, + __m128i __B) +{ + return (__m128i) __builtin_ia32_permvarqi128_mask ((__v16qi) __B, + (__v16qi) __A, + (__v16qi) __W, + (__mmask16) __M); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_permutex2var_epi8 (__m256i __A, __m256i __I, __m256i __B) +{ + return (__m256i) __builtin_ia32_vpermt2varqi256_mask ((__v32qi) __I + /* idx */ , + (__v32qi) __A, + (__v32qi) __B, + (__mmask32) - + 1); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_permutex2var_epi8 (__m256i __A, __mmask32 __U, + __m256i __I, __m256i __B) +{ + return (__m256i) __builtin_ia32_vpermt2varqi256_mask ((__v32qi) __I + /* idx */ , + (__v32qi) __A, + (__v32qi) __B, + (__mmask32) + __U); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask2_permutex2var_epi8 (__m256i __A, __m256i __I, + __mmask32 __U, __m256i __B) +{ + return (__m256i) __builtin_ia32_vpermi2varqi256_mask ((__v32qi) __A, + (__v32qi) __I + /* idx */ , + (__v32qi) __B, + (__mmask32) + __U); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_permutex2var_epi8 (__mmask32 __U, __m256i __A, + __m256i __I, __m256i __B) +{ + return (__m256i) __builtin_ia32_vpermt2varqi256_maskz ((__v32qi) __I + /* idx */ , + (__v32qi) __A, + (__v32qi) __B, + (__mmask32) + __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_permutex2var_epi8 (__m128i __A, __m128i __I, __m128i __B) +{ + return (__m128i) __builtin_ia32_vpermt2varqi128_mask ((__v16qi) __I + /* idx */ , + (__v16qi) __A, + (__v16qi) __B, + (__mmask16) - + 1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_permutex2var_epi8 (__m128i __A, __mmask16 __U, __m128i __I, + __m128i __B) +{ + return (__m128i) __builtin_ia32_vpermt2varqi128_mask ((__v16qi) __I + /* idx */ , + (__v16qi) __A, + (__v16qi) __B, + (__mmask16) + __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask2_permutex2var_epi8 (__m128i __A, __m128i __I, __mmask16 __U, + __m128i __B) +{ + return (__m128i) __builtin_ia32_vpermi2varqi128_mask ((__v16qi) __A, + (__v16qi) __I + /* idx */ , + (__v16qi) __B, + (__mmask16) + __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_permutex2var_epi8 (__mmask16 __U, __m128i __A, __m128i __I, + __m128i __B) +{ + return (__m128i) __builtin_ia32_vpermt2varqi128_maskz ((__v16qi) __I + /* idx */ , + (__v16qi) __A, + (__v16qi) __B, + (__mmask16) + __U); +} + +#ifdef __DISABLE_AVX512VBMIVL__ +#undef __DISABLE_AVX512VBMIVL__ +#pragma GCC pop_options +#endif /* __DISABLE_AVX512VBMIVL__ */ + +#endif /* _AVX512VBMIVLINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/clwbintrin.h b/gcc/config/i386/clwbintrin.h new file mode 100644 index 0000000..9020c95 --- /dev/null +++ b/gcc/config/i386/clwbintrin.h @@ -0,0 +1,49 @@ +/* Copyright (C) 2013 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#if !defined _X86INTRIN_H_INCLUDED +# error "Never use <clwbintrin.h> directly; include <x86intrin.h> instead." +#endif + +#ifndef _CLWBINTRIN_H_INCLUDED +#define _CLWBINTRIN_H_INCLUDED + +#ifndef __CLWB__ +#pragma GCC push_options +#pragma GCC target("clwb") +#define __DISABLE_CLWB__ +#endif /* __CLWB__ */ + +extern __inline void +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_clwb (void *__A) +{ + __builtin_ia32_clwb (__A); +} + +#ifdef __DISABLE_CLWB__ +#undef __DISABLE_CLWB__ +#pragma GCC pop_options +#endif /* __DISABLE_CLWB__ */ + +#endif /* _CLWBINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 133e356..6c6e7f3 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -76,7 +76,10 @@ #define bit_AVX512DQ (1 << 17) #define bit_RDSEED (1 << 18) #define bit_ADX (1 << 19) +#define bit_AVX512IFMA (1 << 21) +#define bit_PCOMMIT (1 << 22) #define bit_CLFLUSHOPT (1 << 23) +#define bit_CLWB (1 << 24) #define bit_AVX512PF (1 << 26) #define bit_AVX512ER (1 << 27) #define bit_AVX512CD (1 << 28) @@ -86,6 +89,7 @@ /* %ecx */ #define bit_PREFETCHWT1 (1 << 0) +#define bit_AVX512VBMI (1 << 1) /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */ #define bit_XSAVEOPT (1 << 0) diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index c913113..a2248ce 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -412,6 +412,8 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0; unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0; unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0; + unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0; + unsigned int has_pcommit = 0; bool arch; @@ -489,12 +491,16 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_avx512pf = ebx & bit_AVX512PF; has_avx512cd = ebx & bit_AVX512CD; has_sha = ebx & bit_SHA; + has_pcommit = ebx & bit_PCOMMIT; has_clflushopt = ebx & bit_CLFLUSHOPT; + has_clwb = ebx & bit_CLWB; has_avx512dq = ebx & bit_AVX512DQ; has_avx512bw = ebx & bit_AVX512BW; has_avx512vl = ebx & bit_AVX512VL; + has_avx512vl = ebx & bit_AVX512IFMA; has_prefetchwt1 = ecx & bit_PREFETCHWT1; + has_avx512vl = ecx & bit_AVX512VBMI; } if (max_level >= 13) @@ -925,6 +931,10 @@ const char *host_detect_local_cpu (int argc, const char **argv) const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq"; const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw"; const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl"; + const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma"; + const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi"; + const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb"; + const char *pcommit = has_pcommit ? " -mpcommit" : " -mno-pcommit"; options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3, sse4a, cx16, sahf, movbe, aes, sha, pclmul, @@ -934,7 +944,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) fxsr, xsave, xsaveopt, avx512f, avx512er, avx512cd, avx512pf, prefetchwt1, clflushopt, xsavec, xsaves, avx512dq, avx512bw, avx512vl, - NULL); + avx512ifma, avx512vbmi, clwb, pcommit, NULL); } done: diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 0a0775d..3ad7d49 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -351,6 +351,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__AVX512BW__"); if (isa_flag & OPTION_MASK_ISA_AVX512VL) def_or_undef (parse_in, "__AVX512VL__"); + if (isa_flag & OPTION_MASK_ISA_AVX512VBMI) + def_or_undef (parse_in, "__AVX512VBMI__"); + if (isa_flag & OPTION_MASK_ISA_AVX512IFMA) + def_or_undef (parse_in, "__AVX512IFMA__"); if (isa_flag & OPTION_MASK_ISA_FMA) def_or_undef (parse_in, "__FMA__"); if (isa_flag & OPTION_MASK_ISA_RTM) @@ -407,6 +411,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__XSAVES__"); if (isa_flag & OPTION_MASK_ISA_MPX) def_or_undef (parse_in, "__MPX__"); + if (isa_flag & OPTION_MASK_ISA_PCOMMIT) + def_or_undef (parse_in, "__PCOMMIT__"); + if (isa_flag & OPTION_MASK_ISA_CLWB) + def_or_undef (parse_in, "__CLWB__"); } diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 3166e03..d76b5af 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2618,6 +2618,8 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, { "-mavx512dq", OPTION_MASK_ISA_AVX512DQ }, { "-mavx512bw", OPTION_MASK_ISA_AVX512BW }, { "-mavx512vl", OPTION_MASK_ISA_AVX512VL }, + { "-mavx512ifma", OPTION_MASK_ISA_AVX512IFMA }, + { "-mavx512vbmi", OPTION_MASK_ISA_AVX512VBMI }, { "-msse4a", OPTION_MASK_ISA_SSE4A }, { "-msse4.2", OPTION_MASK_ISA_SSE4_2 }, { "-msse4.1", OPTION_MASK_ISA_SSE4_1 }, @@ -2655,6 +2657,8 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, { "-mxsavec", OPTION_MASK_ISA_XSAVEC }, { "-mxsaves", OPTION_MASK_ISA_XSAVES }, { "-mmpx", OPTION_MASK_ISA_MPX }, + { "-mclwb", OPTION_MASK_ISA_CLWB }, + { "-mpcommit", OPTION_MASK_ISA_PCOMMIT }, }; /* Flag options. */ @@ -3153,6 +3157,10 @@ ix86_option_override_internal (bool main_args_p, #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50) #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51) #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52) +#define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 53) +#define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 54) +#define PTA_CLWB (HOST_WIDE_INT_1 << 55) +#define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56) #define PTA_CORE2 \ (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \ @@ -3712,6 +3720,12 @@ ix86_option_override_internal (bool main_args_p, if (processor_alias_table[i].flags & PTA_PREFETCHWT1 && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PREFETCHWT1)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1; + if (processor_alias_table[i].flags & PTA_PCOMMIT + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PCOMMIT)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCOMMIT; + if (processor_alias_table[i].flags & PTA_CLWB + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLWB)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB; if (processor_alias_table[i].flags & PTA_CLFLUSHOPT && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLFLUSHOPT)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT; @@ -3733,6 +3747,12 @@ ix86_option_override_internal (bool main_args_p, if (processor_alias_table[i].flags & PTA_MPX && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MPX)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MPX; + if (processor_alias_table[i].flags & PTA_AVX512VBMI + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VBMI)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI; + if (processor_alias_table[i].flags & PTA_AVX512IFMA + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512IFMA)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA; if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) x86_prefetch_sse = true; @@ -4649,6 +4669,10 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[], IX86_ATTR_ISA ("clflushopt", OPT_mclflushopt), IX86_ATTR_ISA ("xsavec", OPT_mxsavec), IX86_ATTR_ISA ("xsaves", OPT_mxsaves), + IX86_ATTR_ISA ("avx512vbmi", OPT_mavx512vbmi), + IX86_ATTR_ISA ("avx512ifma", OPT_mavx512ifma), + IX86_ATTR_ISA ("clwb", OPT_mclwb), + IX86_ATTR_ISA ("pcommit", OPT_mpcommit), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), @@ -30037,6 +30061,37 @@ enum ix86_builtins IX86_BUILTIN_RSQRT28SD, IX86_BUILTIN_RSQRT28SS, + /* AVX-512IFMA */ + IX86_BUILTIN_VPMADD52LUQ512, + IX86_BUILTIN_VPMADD52HUQ512, + IX86_BUILTIN_VPMADD52LUQ256, + IX86_BUILTIN_VPMADD52HUQ256, + IX86_BUILTIN_VPMADD52LUQ128, + IX86_BUILTIN_VPMADD52HUQ128, + IX86_BUILTIN_VPMADD52LUQ512_MASKZ, + IX86_BUILTIN_VPMADD52HUQ512_MASKZ, + IX86_BUILTIN_VPMADD52LUQ256_MASKZ, + IX86_BUILTIN_VPMADD52HUQ256_MASKZ, + IX86_BUILTIN_VPMADD52LUQ128_MASKZ, + IX86_BUILTIN_VPMADD52HUQ128_MASKZ, + + /* AVX-512IFMA */ + IX86_BUILTIN_VPMULTISHIFTQB512, + IX86_BUILTIN_VPMULTISHIFTQB256, + IX86_BUILTIN_VPMULTISHIFTQB128, + IX86_BUILTIN_VPERMVARQI512_MASK, + IX86_BUILTIN_VPERMT2VARQI512, + IX86_BUILTIN_VPERMT2VARQI512_MASKZ, + IX86_BUILTIN_VPERMI2VARQI512, + IX86_BUILTIN_VPERMVARQI256_MASK, + IX86_BUILTIN_VPERMVARQI128_MASK, + IX86_BUILTIN_VPERMT2VARQI256, + IX86_BUILTIN_VPERMT2VARQI256_MASKZ, + IX86_BUILTIN_VPERMT2VARQI128, + IX86_BUILTIN_VPERMT2VARQI128_MASKZ, + IX86_BUILTIN_VPERMI2VARQI256, + IX86_BUILTIN_VPERMI2VARQI128, + /* SHA builtins. */ IX86_BUILTIN_SHA1MSG1, IX86_BUILTIN_SHA1MSG2, @@ -30046,6 +30101,12 @@ enum ix86_builtins IX86_BUILTIN_SHA256MSG2, IX86_BUILTIN_SHA256RNDS2, + /* CLWB instructions. */ + IX86_BUILTIN_CLWB, + + /* PCOMMIT instructions. */ + IX86_BUILTIN_PCOMMIT, + /* CLFLUSHOPT instructions. */ IX86_BUILTIN_CLFLUSHOPT, @@ -30806,6 +30867,9 @@ static const struct builtin_description bdesc_special_args[] = { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI }, { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI }, { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI }, + + /* PCOMMIT. */ + { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID }, }; /* Builtins with variable number of arguments. */ @@ -32707,6 +32771,37 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI }, { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI }, { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI }, + + /* AVX512IFMA */ + { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI }, + { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI }, + { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI }, + { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI }, + { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI }, + { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI }, + { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI }, + { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI }, + { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI }, + { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI }, + { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI }, + { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI }, + + /* AVX512VBMI */ + { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI }, + { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI }, + { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI }, + { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI }, + { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI }, }; /* Builtins with rounding support. */ @@ -33875,6 +33970,10 @@ ix86_init_mmx_sse_builtins (void) def_builtin (OPTION_MASK_ISA_CLFLUSHOPT, "__builtin_ia32_clflushopt", VOID_FTYPE_PCVOID, IX86_BUILTIN_CLFLUSHOPT); + /* CLWB. */ + def_builtin (OPTION_MASK_ISA_CLWB, "__builtin_ia32_clwb", + VOID_FTYPE_PCVOID, IX86_BUILTIN_CLWB); + /* Add FMA4 multi-arg argument instructions */ for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++) { @@ -38594,6 +38693,16 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, emit_insn (gen_sse2_clflush (op0)); return 0; + case IX86_BUILTIN_CLWB: + arg0 = CALL_EXPR_ARG (exp, 0); + op0 = expand_normal (arg0); + icode = CODE_FOR_clwb; + if (!insn_data[icode].operand[0].predicate (op0, Pmode)) + op0 = ix86_zero_extend_to_Pmode (op0); + + emit_insn (gen_clwb (op0)); + return 0; + case IX86_BUILTIN_CLFLUSHOPT: arg0 = CALL_EXPR_ARG (exp, 0); op0 = expand_normal (arg0); @@ -41479,7 +41588,8 @@ ix86_hard_regno_mode_ok (int regno, machine_mode mode) return VALID_FP_MODE_P (mode); if (MASK_REGNO_P (regno)) return (VALID_MASK_REG_MODE (mode) - || (TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE (mode))); + || ((TARGET_AVX512BW || TARGET_AVX512VBMI) + && VALID_MASK_AVX512BW_MODE (mode))); if (BND_REGNO_P (regno)) return VALID_BND_REG_MODE (mode); if (SSE_REGNO_P (regno)) diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 53dfd22..3f5f979 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -77,6 +77,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) #define TARGET_AVX512VL TARGET_ISA_AVX512VL #define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) +#define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI +#define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x) +#define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA +#define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) #define TARGET_FMA TARGET_ISA_FMA #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) #define TARGET_SSE4A TARGET_ISA_SSE4A @@ -146,6 +150,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) #define TARGET_MPX TARGET_ISA_MPX #define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x) +#define TARGET_PCOMMIT TARGET_ISA_PCOMMIT +#define TARGET_PCOMMIT_P(x) TARGET_ISA_PCOMMIT_P(x) +#define TARGET_CLWB TARGET_ISA_CLWB +#define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) #define TARGET_LP64 TARGET_ABI_64 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 203db11..b3b8af6 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -253,6 +253,12 @@ UNSPECV_NLGR + ;; For CLWB support + UNSPECV_CLWB + + ;; For PCOMMIT support + UNSPECV_PCOMMIT + ;; For CLFLUSHOPT support UNSPECV_CLFLUSHOPT ]) @@ -18668,6 +18674,22 @@ [(set_attr "type" "other") (set_attr "length" "3")]) +(define_insn "pcommit" + [(unspec_volatile [(const_int 0)] UNSPECV_PCOMMIT)] + "TARGET_PCOMMIT" + "pcommit" + [(set_attr "type" "other") + (set_attr "length" "4")]) + +(define_insn "clwb" + [(unspec_volatile [(match_operand 0 "address_operand" "p")] + UNSPECV_CLWB)] + "TARGET_CLWB" + "clwb\t%a0" + [(set_attr "type" "sse") + (set_attr "atom_sse_attr" "fence") + (set_attr "memory" "unknown")]) + (define_insn "clflushopt" [(unspec_volatile [(match_operand 0 "address_operand" "p")] UNSPECV_CLFLUSHOPT)] diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 5dfa9bf..c6d6e25 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -653,6 +653,14 @@ mavx512vl Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation +mavx512ifma +Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation + +mavx512vbmi +Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation + mfma Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation @@ -713,6 +721,14 @@ mclflushopt Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save Support CLFLUSHOPT instructions +mclwb +Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save +Support CLWB instructions + +mpcommit +Target Report Mask(ISA_PCOMMIT) Var(ix86_isa_flags) Save +Support PCOMMIT instructions + mfxsr Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save Support FXSAVE and FXRSTOR instructions diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index 5d92182..931ff15 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -60,6 +60,14 @@ #include <avx512vldqintrin.h> +#include <avx512ifmaintrin.h> + +#include <avx512ifmavlintrin.h> + +#include <avx512vbmiintrin.h> + +#include <avx512vbmivlintrin.h> + #include <shaintrin.h> #include <lzcntintrin.h> diff --git a/gcc/config/i386/pcommitintrin.h b/gcc/config/i386/pcommitintrin.h new file mode 100644 index 0000000..b3a802e --- /dev/null +++ b/gcc/config/i386/pcommitintrin.h @@ -0,0 +1,49 @@ +/* Copyright (C) 2013 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#if !defined _X86INTRIN_H_INCLUDED +# error "Never use <pcommitintrin.h> directly; include <x86intrin.h> instead." +#endif + +#ifndef _PCOMMITINTRIN_H_INCLUDED +#define _PCOMMITINTRIN_H_INCLUDED + +#ifndef __PCOMMIT__ +#pragma GCC push_options +#pragma GCC target("pcommit") +#define __DISABLE_PCOMMIT__ +#endif /* __PCOMMIT__ */ + +extern __inline void +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_pcommit (void) +{ + __builtin_ia32_pcommit (); +} + +#ifdef __DISABLE_PCOMMIT__ +#undef __DISABLE_PCOMMIT__ +#pragma GCC pop_options +#endif /* __DISABLE_PCOMMIT__ */ + +#endif /* _PCOMMITINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 13ddd29..ca5d720 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -141,6 +141,13 @@ UNSPEC_REDUCE UNSPEC_FPCLASS UNSPEC_RANGE + + ;; For AVX512IFMA support + UNSPEC_VPMADD52LUQ + UNSPEC_VPMADD52HUQ + + ;; For AVX512VBMI support + UNSPEC_VPMULTISHIFT ]) (define_c_enum "unspecv" [ @@ -175,6 +182,9 @@ [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") V32HI (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")]) +(define_mode_iterator VI1_AVX512VL + [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")]) + ;; All vector modes (define_mode_iterator V [(V32QI "TARGET_AVX") V16QI @@ -16465,6 +16475,18 @@ (set_attr "mode" "<sseinsnmode>")]) (define_insn "<avx512>_permvar<mode><mask_name>" + [(set (match_operand:VI1_AVX512VL 0 "register_operand" "=v") + (unspec:VI1_AVX512VL + [(match_operand:VI1_AVX512VL 1 "nonimmediate_operand" "vm") + (match_operand:<sseintvecmode> 2 "register_operand" "v")] + UNSPEC_VPERMVAR))] + "TARGET_AVX512VBMI && <mask_mode512bit_condition>" + "vperm<ssemodesuffix>\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}" + [(set_attr "type" "sselog") + (set_attr "prefix" "<mask_prefix2>") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn "<avx512>_permvar<mode><mask_name>" [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") (unspec:VI2_AVX512VL [(match_operand:VI2_AVX512VL 1 "nonimmediate_operand" "vm") @@ -17007,6 +17029,20 @@ }) (define_expand "<avx512>_vpermi2var<mode>3_maskz" + [(match_operand:VI1_AVX512VL 0 "register_operand") + (match_operand:VI1_AVX512VL 1 "register_operand") + (match_operand:<sseintvecmode> 2 "register_operand") + (match_operand:VI1_AVX512VL 3 "nonimmediate_operand") + (match_operand:<avx512fmaskmode> 4 "register_operand")] + "TARGET_AVX512VBMI" +{ + emit_insn (gen_<avx512>_vpermi2var<mode>3_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (<MODE>mode), operands[4])); + DONE; +}) + +(define_expand "<avx512>_vpermi2var<mode>3_maskz" [(match_operand:VI2_AVX512VL 0 "register_operand" "=v") (match_operand:VI2_AVX512VL 1 "register_operand" "v") (match_operand:<sseintvecmode> 2 "register_operand" "0") @@ -17034,6 +17070,19 @@ (set_attr "mode" "<sseinsnmode>")]) (define_insn "<avx512>_vpermi2var<mode>3<sd_maskz_name>" + [(set (match_operand:VI1_AVX512VL 0 "register_operand" "=v") + (unspec:VI1_AVX512VL + [(match_operand:VI1_AVX512VL 1 "register_operand" "v") + (match_operand:<sseintvecmode> 2 "register_operand" "0") + (match_operand:VI1_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPERMI2))] + "TARGET_AVX512VBMI" + "vpermi2<ssemodesuffix>\t{%3, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %3}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn "<avx512>_vpermi2var<mode>3<sd_maskz_name>" [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") (unspec:VI2_AVX512VL [(match_operand:VI2_AVX512VL 1 "register_operand" "v") @@ -17063,6 +17112,22 @@ (set_attr "mode" "<sseinsnmode>")]) (define_insn "<avx512>_vpermi2var<mode>3_mask" + [(set (match_operand:VI1_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI1_AVX512VL + (unspec:VI1_AVX512VL + [(match_operand:VI1_AVX512VL 1 "register_operand" "v") + (match_operand:<sseintvecmode> 2 "register_operand" "0") + (match_operand:VI1_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPERMI2_MASK) + (match_dup 0) + (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] + "TARGET_AVX512VBMI" + "vpermi2<ssemodesuffix>\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn "<avx512>_vpermi2var<mode>3_mask" [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") (vec_merge:VI2_AVX512VL (unspec:VI2_AVX512VL @@ -17093,6 +17158,20 @@ }) (define_expand "<avx512>_vpermt2var<mode>3_maskz" + [(match_operand:VI1_AVX512VL 0 "register_operand" "=v") + (match_operand:<sseintvecmode> 1 "register_operand" "v") + (match_operand:VI1_AVX512VL 2 "register_operand" "0") + (match_operand:VI1_AVX512VL 3 "nonimmediate_operand" "vm") + (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")] + "TARGET_AVX512VBMI" +{ + emit_insn (gen_<avx512>_vpermt2var<mode>3_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (<MODE>mode), operands[4])); + DONE; +}) + +(define_expand "<avx512>_vpermt2var<mode>3_maskz" [(match_operand:VI2_AVX512VL 0 "register_operand" "=v") (match_operand:<sseintvecmode> 1 "register_operand" "v") (match_operand:VI2_AVX512VL 2 "register_operand" "0") @@ -17120,6 +17199,19 @@ (set_attr "mode" "<sseinsnmode>")]) (define_insn "<avx512>_vpermt2var<mode>3<sd_maskz_name>" + [(set (match_operand:VI1_AVX512VL 0 "register_operand" "=v") + (unspec:VI1_AVX512VL + [(match_operand:<sseintvecmode> 1 "register_operand" "v") + (match_operand:VI1_AVX512VL 2 "register_operand" "0") + (match_operand:VI1_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPERMT2))] + "TARGET_AVX512VBMI" + "vpermt2<ssemodesuffix>\t{%3, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %3}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn "<avx512>_vpermt2var<mode>3<sd_maskz_name>" [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") (unspec:VI2_AVX512VL [(match_operand:<sseintvecmode> 1 "register_operand" "v") @@ -17149,6 +17241,22 @@ (set_attr "mode" "<sseinsnmode>")]) (define_insn "<avx512>_vpermt2var<mode>3_mask" + [(set (match_operand:VI1_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI1_AVX512VL + (unspec:VI1_AVX512VL + [(match_operand:<sseintvecmode> 1 "register_operand" "v") + (match_operand:VI1_AVX512VL 2 "register_operand" "0") + (match_operand:VI1_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPERMT2) + (match_dup 2) + (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] + "TARGET_AVX512VBMI" + "vpermt2<ssemodesuffix>\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn "<avx512>_vpermt2var<mode>3_mask" [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") (vec_merge:VI2_AVX512VL (unspec:VI2_AVX512VL @@ -18450,3 +18558,79 @@ emit_move_insn (op0, op1); DONE; }) + +(define_int_iterator VPMADD52 + [UNSPEC_VPMADD52LUQ + UNSPEC_VPMADD52HUQ]) + +(define_int_attr vpmadd52type + [(UNSPEC_VPMADD52LUQ "luq") (UNSPEC_VPMADD52HUQ "huq")]) + +(define_expand "vpamdd52huq<mode>_maskz" + [(match_operand:VI8_AVX512VL 0 "register_operand") + (match_operand:VI8_AVX512VL 1 "register_operand") + (match_operand:VI8_AVX512VL 2 "register_operand") + (match_operand:VI8_AVX512VL 3 "nonimmediate_operand") + (match_operand:<avx512fmaskmode> 4 "register_operand")] + "TARGET_AVX512IFMA" +{ + emit_insn (gen_vpamdd52huq<mode>_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (<MODE>mode), operands[4])); + DONE; +}) + +(define_expand "vpamdd52luq<mode>_maskz" + [(match_operand:VI8_AVX512VL 0 "register_operand") + (match_operand:VI8_AVX512VL 1 "register_operand") + (match_operand:VI8_AVX512VL 2 "register_operand") + (match_operand:VI8_AVX512VL 3 "nonimmediate_operand") + (match_operand:<avx512fmaskmode> 4 "register_operand")] + "TARGET_AVX512IFMA" +{ + emit_insn (gen_vpamdd52luq<mode>_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (<MODE>mode), operands[4])); + DONE; +}) + +(define_insn "vpamdd52<vpmadd52type><mode><sd_maskz_name>" + [(set (match_operand:VI8_AVX512VL 0 "register_operand" "=v") + (unspec:VI8_AVX512VL + [(match_operand:VI8_AVX512VL 1 "register_operand" "0") + (match_operand:VI8_AVX512VL 2 "register_operand" "v") + (match_operand:VI8_AVX512VL 3 "nonimmediate_operand" "vm")] + VPMADD52))] + "TARGET_AVX512IFMA" + "vpmadd52<vpmadd52type>\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}" + [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn "vpamdd52<vpmadd52type><mode>_mask" + [(set (match_operand:VI8_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI8_AVX512VL + (unspec:VI8_AVX512VL + [(match_operand:VI8_AVX512VL 1 "register_operand" "0") + (match_operand:VI8_AVX512VL 2 "register_operand" "v") + (match_operand:VI8_AVX512VL 3 "nonimmediate_operand" "vm")] + VPMADD52) + (match_dup 1) + (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] + "TARGET_AVX512IFMA" + "vpmadd52<vpmadd52type>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" + [(set_attr "type" "ssemuladd") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn "vpmultishiftqb<mode><mask_name>" + [(set (match_operand:VI1_AVX512VL 0 "register_operand" "=v") + (unspec:VI1_AVX512VL + [(match_operand:VI1_AVX512VL 1 "register_operand" "v") + (match_operand:VI1_AVX512VL 2 "nonimmediate_operand" "vm")] + UNSPEC_VPMULTISHIFT))] + "TARGET_AVX512VBMI" + "vpmultishiftqb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) diff --git a/gcc/config/i386/x86intrin.h b/gcc/config/i386/x86intrin.h index c84ab88..fdb613f 100644 --- a/gcc/config/i386/x86intrin.h +++ b/gcc/config/i386/x86intrin.h @@ -75,6 +75,10 @@ #include <adxintrin.h> +#include <clwbintrin.h> + +#include <pcommitintrin.h> + #include <clflushoptintrin.h> #include <xsavesintrin.h> diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C index d642acc..4f77dd7 100644 --- a/gcc/testsuite/g++.dg/other/i386-2.C +++ b/gcc/testsuite/g++.dg/other/i386-2.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl" } */ +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C index 6d3e24f..53b90b8 100644 --- a/gcc/testsuite/g++.dg/other/i386-3.C +++ b/gcc/testsuite/g++.dg/other/i386-3.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl" } */ +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/gcc.target/i386/avx512f-helper.h b/gcc/testsuite/gcc.target/i386/avx512f-helper.h index 04a1a89..e270cd2 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-helper.h +++ b/gcc/testsuite/gcc.target/i386/avx512f-helper.h @@ -20,6 +20,10 @@ #include "avx512bw-check.h" #elif defined (AVX512VL) #include "avx512vl-check.h" +#elif defined (AVX512IFMA) +#include "avx512ifma-check.h" +#elif defined (AVX512VBMI) +#include "avx512vbmi-check.h" #endif /* Macros expansion. */ @@ -125,6 +129,12 @@ avx512bw_test (void) { test_512 (); } #elif defined (AVX512VL) void avx512vl_test (void) { test_256 (); test_128 (); } +#elif defined (AVX512IFMA) +void +avx512ifma_test (void) { test_512 (); } +#elif defined (AVX512VBMI) +void +avx512vbmi_test (void) { test_512 (); } #endif #endif /* AVX512F_HELPER_INCLUDED */ diff --git a/gcc/testsuite/gcc.target/i386/avx512ifma-check.h b/gcc/testsuite/gcc.target/i386/avx512ifma-check.h new file mode 100644 index 0000000..9c17a54 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512ifma-check.h @@ -0,0 +1,46 @@ +#include <stdlib.h> +#include "cpuid.h" +#include "m512-check.h" +#include "avx512f-os-support.h" + +static void avx512ifma_test (void); + +static void __attribute__ ((noinline)) do_test (void) +{ + avx512ifma_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + if ((ecx & bit_OSXSAVE) == (bit_OSXSAVE)) + { + if (__get_cpuid_max (0, NULL) < 7) + return 0; + + __cpuid_count (7, 0, eax, ebx, ecx, edx); + + if ((avx512f_os_support ()) && ((ebx & bit_AVX512IFMA) == bit_AVX512IFMA)) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + return 0; + } +#ifdef DEBUG + printf ("SKIPPED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddhuq-1.c b/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddhuq-1.c new file mode 100644 index 0000000..5bc3311 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddhuq-1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512ifma -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vpmadd52huq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpmadd52huq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpmadd52huq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ +/* { dg-final { scan-assembler-times "vpmadd52huq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpmadd52huq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpmadd52huq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ +/* { dg-final { scan-assembler-times "vpmadd52huq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpmadd52huq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpmadd52huq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ + +#include <immintrin.h> + +volatile __m512i _x1, _y1, _z1; +volatile __m256i _x2, _y2, _z2; +volatile __m128i _x3, _y3, _z3; + +void extern +avx512ifma_test (void) +{ + _x3 = _mm_madd52hi_epu64 (_x3, _y3, _z3); + _x3 = _mm_mask_madd52hi_epu64 (_x3, 2, _y3, _z3); + _x3 = _mm_maskz_madd52hi_epu64 (2, _x3, _y3, _z3); + _x2 = _mm256_madd52hi_epu64 (_x2, _y2, _z2); + _x2 = _mm256_mask_madd52hi_epu64 (_x2, 3, _y2, _z2); + _x2 = _mm256_maskz_madd52hi_epu64 (3, _x2, _y2, _z2); + _x1 = _mm512_madd52hi_epu64 (_x1, _y1, _z1); + _x1 = _mm512_mask_madd52hi_epu64 (_x1, 3, _y1, _z1); + _x1 = _mm512_maskz_madd52hi_epu64 (3, _x1, _y1, _z1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddhuq-2.c b/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddhuq-2.c new file mode 100644 index 0000000..edb28cb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddhuq-2.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512ifma -DAVX512IFMA" } */ +/* { dg-require-effective-target avx512ifma } */ + +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 64) +#include "avx512f-mask-type.h" + +void +CALC (long long *r, long long *s1, long long *s2, long long *s3) +{ + int i; + long long a, b; + + for (i = 0; i < SIZE; i++) + { + /* Simulate higher 52 bits out of 104 bit, + by shifting opernads with 0 in lower 26 bits. */ + a = s2[i] >> 26; + b = s3[i] >> 26; + r[i] = a * b + s1[i]; + } +} + +void +TEST (void) +{ + UNION_TYPE (AVX512F_LEN, i_q) src1, src2, dst1, dst2, dst3; + long long dst_ref[SIZE]; + int i; + MASK_TYPE mask = MASK_VALUE; + + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 15 + 3467 * i; + src2.a[i] = 9217 + i; + src1.a[i] = src1.a[i] << 26; + src1.a[i] = src1.a[i] << 26; + src1.a[i] &= ((1LL << 52) - 1); + src2.a[i] &= ((1LL << 52) - 1); + dst1.a[i] = DEFAULT_VALUE; + dst2.a[i] = DEFAULT_VALUE; + dst3.a[i] = DEFAULT_VALUE; + } + + CALC (dst_ref, dst1.a, src1.a, src2.a); + dst1.x = INTRINSIC (_madd52hi_epu64) (dst1.x, src1.x, src2.x); + dst2.x = INTRINSIC (_mask_madd52hi_epu64) (dst2.x, mask, src1.x, src2.x); + dst3.x = INTRINSIC (_maskz_madd52hi_epu64) (mask, dst3.x, src1.x, src2.x); + + if (UNION_CHECK (AVX512F_LEN, i_q) (dst1, dst_ref)) + abort (); + + MASK_MERGE (i_q) (dst_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_q) (dst2, dst_ref)) + abort (); + + MASK_ZERO (i_q) (dst_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_q) (dst3, dst_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddluq-1.c b/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddluq-1.c new file mode 100644 index 0000000..5a17cf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddluq-1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512ifma -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vpmadd52luq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpmadd52luq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpmadd52luq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ +/* { dg-final { scan-assembler-times "vpmadd52luq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpmadd52luq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpmadd52luq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ +/* { dg-final { scan-assembler-times "vpmadd52luq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpmadd52luq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpmadd52luq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ + +#include <immintrin.h> + +volatile __m512i _x1, _y1, _z1; +volatile __m256i _x2, _y2, _z2; +volatile __m128i _x3, _y3, _z3; + +void extern +avx512ifma_test (void) +{ + _x3 = _mm_madd52lo_epu64 (_x3, _y3, _z3); + _x3 = _mm_mask_madd52lo_epu64 (_x3, 2, _y3, _z3); + _x3 = _mm_maskz_madd52lo_epu64 (2, _x3, _y3, _z3); + _x2 = _mm256_madd52lo_epu64 (_x2, _y2, _z2); + _x2 = _mm256_mask_madd52lo_epu64 (_x2, 3, _y2, _z2); + _x2 = _mm256_maskz_madd52lo_epu64 (3, _x2, _y2, _z2); + _x1 = _mm512_madd52lo_epu64 (_x1, _y1, _z1); + _x1 = _mm512_mask_madd52lo_epu64 (_x1, 3, _y1, _z1); + _x1 = _mm512_maskz_madd52lo_epu64 (3, _x1, _y1, _z1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddluq-2.c b/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddluq-2.c new file mode 100644 index 0000000..6937d13 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512ifma-vpmaddluq-2.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512ifma -DAVX512IFMA" } */ +/* { dg-require-effective-target avx512ifma } */ + +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 64) +#include "avx512f-mask-type.h" + +void +CALC (unsigned long long *r, unsigned long long *s1, + unsigned long long *s2, unsigned long long *s3) +{ + int i; + + /* Valid, because values are less than 1 << 26. */ + for (i = 0; i < SIZE; i++) + r[i] = s2[i] * s3[i] + s1[i]; +} + +void +TEST (void) +{ + UNION_TYPE (AVX512F_LEN, i_q) src1, src2, dst1, dst2, dst3; + unsigned long long dst_ref[SIZE]; + int i; + MASK_TYPE mask = MASK_VALUE; + + for (i = 0; i < SIZE; i++) + { + src1.a[i] = i + 50; + src2.a[i] = i + 100; + dst1.a[i] = DEFAULT_VALUE; + dst2.a[i] = DEFAULT_VALUE; + dst3.a[i] = DEFAULT_VALUE; + } + + CALC (dst_ref, dst1.a, src1.a, src2.a); + dst1.x = INTRINSIC (_madd52lo_epu64) (dst1.x, src1.x, src2.x); + dst2.x = INTRINSIC (_mask_madd52lo_epu64) (dst2.x, mask, src1.x, src2.x); + dst3.x = INTRINSIC (_maskz_madd52lo_epu64) (mask, dst3.x, src1.x, src2.x); + + if (UNION_CHECK (AVX512F_LEN, i_q) (dst1, dst_ref)) + abort (); + + MASK_MERGE (i_q) (dst_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_q) (dst2, dst_ref)) + abort (); + + MASK_ZERO (i_q) (dst_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_q) (dst3, dst_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vbmi-check.h b/gcc/testsuite/gcc.target/i386/avx512vbmi-check.h new file mode 100644 index 0000000..591ff06 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vbmi-check.h @@ -0,0 +1,46 @@ +#include <stdlib.h> +#include "cpuid.h" +#include "m512-check.h" +#include "avx512f-os-support.h" + +static void avx512vbmi_test (void); + +static void __attribute__ ((noinline)) do_test (void) +{ + avx512vbmi_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + if ((ecx & bit_OSXSAVE) == (bit_OSXSAVE)) + { + if (__get_cpuid_max (0, NULL) < 7) + return 0; + + __cpuid_count (7, 0, eax, ebx, ecx, edx); + + if ((avx512f_os_support ()) && ((ebx & bit_AVX512VBMI) == bit_AVX512VBMI)) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + return 0; + } +#ifdef DEBUG + printf ("SKIPPED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermb-1.c b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermb-1.c new file mode 100644 index 0000000..59e568c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermb-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vbmi -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vpermb\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpermb\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpermb\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ +/* { dg-final { scan-assembler-times "vpermb\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\{\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpermb\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpermb\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ +/* { dg-final { scan-assembler-times "vpermb\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpermb\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpermb\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ + +#include <immintrin.h> + +volatile __m512i x1; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask64 m1; +volatile __mmask32 m2; +volatile __mmask16 m3; + +void extern +avx512bw_test (void) +{ + x1 = _mm512_permutexvar_epi8 (x1, x1); + x1 = _mm512_maskz_permutexvar_epi8 (m1, x1, x1); + x1 = _mm512_mask_permutexvar_epi8 (x1, m1, x1, x1); + x2 = _mm256_permutexvar_epi8 (x2, x2); + x2 = _mm256_maskz_permutexvar_epi8 (m2, x2, x2); + x2 = _mm256_mask_permutexvar_epi8 (x2, m2, x2, x2); + x3 = _mm_permutexvar_epi8 (x3, x3); + x3 = _mm_maskz_permutexvar_epi8 (m3, x3, x3); + x3 = _mm_mask_permutexvar_epi8 (x3, m3, x3, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermb-2.c b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermb-2.c new file mode 100644 index 0000000..fa22fd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermb-2.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vbmi -DAVX512VBMI" } */ +/* { dg-require-effective-target avx512vbmi } */ + +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 8) +#include "avx512f-mask-type.h" + +void +CALC (char *ind, char *src, char *res) +{ + int i; + + for (i = 0; i < SIZE; i++) + { + res[i] = src[ind[i] & (SIZE - 1)]; + } +} + +void +TEST (void) +{ + UNION_TYPE (AVX512F_LEN, i_b) s1, s2, res1, res2, res3; + char res_ref[SIZE]; + MASK_TYPE mask = MASK_VALUE; + int i; + + for (i = 0; i < SIZE; i++) + { + s1.a[i] = i * i * i; + s2.a[i] = i + 20; + res2.a[i] = DEFAULT_VALUE; + } + + res1.x = INTRINSIC (_permutexvar_epi8) (s1.x, s2.x); + res2.x = INTRINSIC (_mask_permutexvar_epi8) (res2.x, mask, s1.x, s2.x); + res3.x = INTRINSIC (_maskz_permutexvar_epi8) (mask, s1.x, s2.x); + CALC (s1.a, s2.a, res_ref); + + if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref)) + abort (); + + MASK_MERGE (i_b)(res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref)) + abort (); + + MASK_ZERO (i_b)(res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermi2b-1.c b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermi2b-1.c new file mode 100644 index 0000000..f760c76 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermi2b-1.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vbmi -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vpermi2b\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpermi2b\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpermi2b\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ + +#include <immintrin.h> + +volatile __m512i x3; +volatile __m256i x2; +volatile __m128i x1; +volatile __m512i z; +volatile __m256i y; +volatile __m128i x; +volatile __mmask32 m3; +volatile __mmask16 m2; +volatile __mmask8 m1; + +void extern +avx512bw_test (void) +{ + x3 = _mm512_mask2_permutex2var_epi8 (x3, z, m3, x3); + x2 = _mm256_mask2_permutex2var_epi8 (x2, y, m2, x2); + x1 = _mm_mask2_permutex2var_epi8 (x1, x, m1, x1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermi2b-2.c b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermi2b-2.c new file mode 100644 index 0000000..694b23b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermi2b-2.c @@ -0,0 +1,58 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vbmi -DAVX512VBMI" } */ +/* { dg-require-effective-target avx512vbmi } */ + +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 8) +#include "math.h" +#include "values.h" +#include "avx512f-mask-type.h" + +#define NUM 32 + +void +CALC (char *dst, char *src1, char *ind, char *src2) +{ + int i; + + for (i = 0; i < SIZE; i++) + { + unsigned long long offset = ind[i] & (SIZE - 1); + unsigned long long cond = ind[i] & SIZE; + + dst[i] = cond ? src2[offset] : src1[offset]; + } +} + +void +TEST (void) +{ + int i, j; + UNION_TYPE (AVX512F_LEN, i_b) s1, s2, res, ind; + char res_ref[SIZE]; + + MASK_TYPE mask = MASK_VALUE; + + for (i = 0; i < NUM; i++) + { + for (j = 0; j < SIZE; j++) + { + ind.a[j] = DEFAULT_VALUE; + s1.a[j] = i * 2 * j + 1; + s2.a[j] = i * 2 * j; + + res.a[j] = DEFAULT_VALUE; + } + + CALC (res_ref, s1.a, ind.a, s2.a); + + res.x = + INTRINSIC (_mask2_permutex2var_epi8) (s1.x, ind.x, mask, + s2.x); + + MASK_MERGE (i_b) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_b) (res, res_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermt2b-1.c b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermt2b-1.c new file mode 100644 index 0000000..2e67a54 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermt2b-1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vbmi -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vpermt2b\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpermt2b\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 3 } } * +/* { dg-final { scan-assembler-times "vpermt2b\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpermt2b\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpermt2b\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpermt2b\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpermt2b\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ +/* { dg-final { scan-assembler-times "vpermt2b\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ +/* { dg-final { scan-assembler-times "vpermt2b\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ + +#include <immintrin.h> + +volatile __m512i x3; +volatile __m256i x2; +volatile __m128i x1; +volatile __m512i z; +volatile __m256i y; +volatile __m128i x; +volatile __mmask32 m3; +volatile __mmask16 m2; +volatile __mmask8 m1; + +void extern +avx512bw_test (void) +{ + x3 = _mm512_permutex2var_epi8 (x3, z, x3); + x3 = _mm512_mask_permutex2var_epi8 (x3, m3, z, x3); + x3 = _mm512_maskz_permutex2var_epi8 (m3, x3, z, x3); + x2 = _mm256_permutex2var_epi8 (x2, y, x2); + x2 = _mm256_mask_permutex2var_epi8 (x2, m2, y, x2); + x2 = _mm256_maskz_permutex2var_epi8 (m2, x2, y, x2); + x1 = _mm_permutex2var_epi8 (x1, x, x1); + x1 = _mm_mask_permutex2var_epi8 (x1, m1, x, x1); + x1 = _mm_maskz_permutex2var_epi8 (m1, x1, x, x1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermt2b-2.c b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermt2b-2.c new file mode 100644 index 0000000..c9f46596 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpermt2b-2.c @@ -0,0 +1,70 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vbmi -DAVX512VBMI" } */ +/* { dg-require-effective-target avx512vbmi } */ + +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 8) +#include "math.h" +#include "values.h" +#include "avx512f-mask-type.h" + +#define NUM 32 + +void +CALC (char *dst, char *src1, char *ind, char *src2) +{ + int i; + + for (i = 0; i < SIZE; i++) + { + unsigned long long offset = ind[i] & (SIZE - 1); + unsigned long long cond = ind[i] & SIZE; + + dst[i] = cond ? src2[offset] : src1[offset]; + } +} + +void +TEST (void) +{ + int i, j; + UNION_TYPE (AVX512F_LEN, i_b) s1, s2, res1, res2, res3, ind; + char res_ref[SIZE]; + + MASK_TYPE mask = MASK_VALUE; + + for (i = 0; i < NUM; i++) + { + for (j = 0; j < SIZE; j++) + { + ind.a[j] = i * (j << 1); + s1.a[j] = DEFAULT_VALUE; + s2.a[j] = 1.5 * i * 2 * j; + + res1.a[j] = DEFAULT_VALUE; + res2.a[j] = DEFAULT_VALUE; + res3.a[j] = DEFAULT_VALUE; + } + + CALC (res_ref, s1.a, ind.a, s2.a); + + res1.x = INTRINSIC (_permutex2var_epi8) (s1.x, ind.x, s2.x); + res2.x = + INTRINSIC (_mask_permutex2var_epi8) (s1.x, mask, ind.x, s2.x); + res3.x = + INTRINSIC (_maskz_permutex2var_epi8) (mask, s1.x, ind.x, + s2.x); + + if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref)) + abort (); + + MASK_MERGE (i_b) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref)) + abort (); + + MASK_ZERO (i_b) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref)) + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vbmi-vpmultishiftqb-1.c b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpmultishiftqb-1.c new file mode 100644 index 0000000..145591c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpmultishiftqb-1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vbmi -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vpmultishiftqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpmultishiftqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpmultishiftqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ +/* { dg-final { scan-assembler-times "vpmultishiftqb\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpmultishiftqb\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpmultishiftqb\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ +/* { dg-final { scan-assembler-times "vpmultishiftqb\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "vpmultishiftqb\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */ +/* { dg-final { scan-assembler-times "vpmultishiftqb\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */ + +#include <immintrin.h> + +volatile __m512i _x1, _y1, _z1; +volatile __m256i _x2, _y2, _z2; +volatile __m128i _x3, _y3, _z3; + +void extern +avx512vbmi_test (void) +{ + _x3 = _mm_multishift_epi64_epi8 (_y3, _z3); + _x3 = _mm_mask_multishift_epi64_epi8 (_x3, 2, _y3, _z3); + _x3 = _mm_maskz_multishift_epi64_epi8 (2, _y3, _z3); + _x2 = _mm256_multishift_epi64_epi8 (_y2, _z2); + _x2 = _mm256_mask_multishift_epi64_epi8 (_x2, 3, _y2, _z2); + _x2 = _mm256_maskz_multishift_epi64_epi8 (3, _y2, _z2); + _x1 = _mm512_multishift_epi64_epi8 (_y1, _z1); + _x1 = _mm512_mask_multishift_epi64_epi8 (_x1, 3, _y1, _z1); + _x1 = _mm512_maskz_multishift_epi64_epi8 (3, _y1, _z1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vbmi-vpmultishiftqb-2.c b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpmultishiftqb-2.c new file mode 100644 index 0000000..936d938 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vbmi-vpmultishiftqb-2.c @@ -0,0 +1,68 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vbmi -DAVX512VBMI" } */ +/* { dg-require-effective-target avx512vbmi } */ + +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 8) +#include "avx512f-mask-type.h" + +void +CALC (char *r, char *s1, char *s2) +{ + int i, j, k; + long long a, b, ctrl; + + for (i = 0; i < SIZE / sizeof (long long); i++) + { + union + { + long long x; + char a[sizeof(long long)]; + } src; + + for (j = 0; j < sizeof (long long); j++) + src.a[j] = s2[i * sizeof (long long) + j]; + for (j = 0; j < sizeof (long long); j++) + { + ctrl = s1[i * sizeof (long long) + j] & ((1 << sizeof (long long)) - 1); + r[i * sizeof (long long) + j] = 0; + for (k = 0; k < 8; k++) + { + r[i * sizeof (long long) + j] |= ((src.x >> ((ctrl + k) % (sizeof (long long) * 8))) & 1) << k; + } + } + } +} + +void +TEST (void) +{ + UNION_TYPE (AVX512F_LEN, i_b) src1, src2, dst1, dst2, dst3; + char dst_ref[SIZE]; + int i; + MASK_TYPE mask = MASK_VALUE; + + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 15 + 3467 * i; + src2.a[i] = 9217 + i; + dst2.a[i] = DEFAULT_VALUE; + } + + CALC (dst_ref, src1.a, src2.a); + dst1.x = INTRINSIC (_multishift_epi64_epi8) (src1.x, src2.x); + dst2.x = INTRINSIC (_mask_multishift_epi64_epi8) (dst2.x, mask, src1.x, src2.x); + dst3.x = INTRINSIC (_maskz_multishift_epi64_epi8) (mask, src1.x, src2.x); + + if (UNION_CHECK (AVX512F_LEN, i_b) (dst1, dst_ref)) + abort (); + + MASK_MERGE (i_b) (dst_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_b) (dst2, dst_ref)) + abort (); + + MASK_ZERO (i_b) (dst_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_b) (dst3, dst_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpermb-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpermb-2.c new file mode 100644 index 0000000..377f34e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpermb-2.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vbmi -mavx512vl -DAVX512VL" } */ +/* { dg-require-effective-target avx512vl } */ + +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512vbmi-vpermb-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512vbmi-vpermb-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpermi2b-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpermi2b-2.c new file mode 100644 index 0000000..bd5dfc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpermi2b-2.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vbmi -mavx512vl -DAVX512VL" } */ +/* { dg-require-effective-target avx512vl } */ + +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512vbmi-vpermi2b-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512vbmi-vpermi2b-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpermt2b-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpermt2b-2.c new file mode 100644 index 0000000..a83eeb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpermt2b-2.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vbmi -mavx512vl -DAVX512VL" } */ +/* { dg-require-effective-target avx512vl } */ + +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512vbmi-vpermt2b-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512vbmi-vpermt2b-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpmaddhuq-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpmaddhuq-2.c new file mode 100644 index 0000000..92d1bf7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpmaddhuq-2.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512ifma -mavx512vl -DAVX512VL" } */ +/* { dg-require-effective-target avx512vl } */ + +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512ifma-vpmaddhuq-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512ifma-vpmaddhuq-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpmaddluq-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpmaddluq-2.c new file mode 100644 index 0000000..6698ad2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpmaddluq-2.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512ifma -mavx512vl -DAVX512VL" } */ +/* { dg-require-effective-target avx512vl } */ + +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512ifma-vpmaddluq-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512ifma-vpmaddluq-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpmultishiftqb-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpmultishiftqb-2.c new file mode 100644 index 0000000..d215e23 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpmultishiftqb-2.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vbmi -mavx512vl -DAVX512VL" } */ +/* { dg-require-effective-target avx512vl } */ + +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512vbmi-vpmultishiftqb-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512vbmi-vpmultishiftqb-2.c" diff --git a/gcc/testsuite/gcc.target/i386/clwb-1.c b/gcc/testsuite/gcc.target/i386/clwb-1.c new file mode 100644 index 0000000..d6f5023 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/clwb-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mclwb" } */ +/* { dg-final { scan-assembler "clwb\[ \\t\]" } } */ + +#include "x86intrin.h" + +void +test_clwb (void *__A) +{ + _mm_clwb (__A); +} diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp index 4fcb8a6..ca5ef06 100644 --- a/gcc/testsuite/gcc.target/i386/i386.exp +++ b/gcc/testsuite/gcc.target/i386/i386.exp @@ -350,6 +350,36 @@ proc check_effective_target_avx512bw { } { } "-mavx512bw" ] } +# Return 1 if avx512ifma instructions can be compiled. +proc check_effective_target_avx512ifma { } { + return [check_no_compiler_messages avx512ifma object { + typedef long long __v8di __attribute__ ((__vector_size__ (64))); + __v8di + _mm512_madd52lo_epu64 (__v8di __X, __v8di __Y, __v8di __Z) + { + return (__v8di) __builtin_ia32_vpmadd52luq512_mask ((__v8di) __X, + (__v8di) __Y, + (__v8di) __Z, + -1); + } + } "-mavx512ifma" ] +} + +# Return 1 if avx512vbmi instructions can be compiled. +proc check_effective_target_avx512vbmi { } { + return [check_no_compiler_messages avx512vbmi object { + typedef char __v64qi __attribute__ ((__vector_size__ (64))); + __v64qi + _mm512_multishift_epi64_epi8 (__v64qi __X, __v64qi __Y) + { + return (__v64qi) __builtin_ia32_vpmultishiftqb512_mask ((__v64qi) __X, + (__v64qi) __Y, + (__v64qi) __Y, + -1); + } + } "-mavx512vbmi" ] +} + # If a testcase doesn't have special options, use these. global DEFAULT_CFLAGS if ![info exists DEFAULT_CFLAGS] then { diff --git a/gcc/testsuite/gcc.target/i386/pcommit-1.c b/gcc/testsuite/gcc.target/i386/pcommit-1.c new file mode 100644 index 0000000..dc4bc9d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pcommit-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mpcommit" } */ +/* { dg-final { scan-assembler "pcommit" } } */ + +#include "x86intrin.h" + +void +test_pcommit () +{ + _mm_pcommit (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index 67bcf48..bdb0e10 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -3,7 +3,7 @@ popcntintrin.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512ifma -mclwb -mpcommit" } */ #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index ec8b56a..104c63e 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512ifma -mclwb -mpcommit" } */ #include <mm_malloc.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index a2a4f73..f3f6c5c 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit" } */ /* { dg-add-options bind_pic_locally } */ #include <mm_malloc.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 1d1ed7b..0d7bd16 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -100,7 +100,7 @@ #ifndef DIFFERENT_PRAGMAS -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512ifma") #endif /* Following intrinsics require immediate arguments. They @@ -215,7 +215,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */ #ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq") +#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi") #endif #include <immintrin.h> test_1 (_cvtss_sh, unsigned short, float, 1) @@ -695,7 +695,7 @@ test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1) /* x86intrin.h (FMA4/XOP/LWP/BMI/BMI2/TBM/LZCNT/FMA). */ #ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw,adx,fxsr,xsaveopt,xsavec,xsaves,clflushopt") +#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw,adx,fxsr,xsaveopt,xsavec,xsaves,clflushopt,clwb,pcommit") #endif #include <x86intrin.h> /* xopintrin.h */ diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index f54f98d..9f81a8a 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -594,7 +594,7 @@ #define __builtin_ia32_extracti64x2_256_mask(A, E, C, D) __builtin_ia32_extracti64x2_256_mask(A, 1, C, D) #define __builtin_ia32_extractf64x2_256_mask(A, E, C, D) __builtin_ia32_extractf64x2_256_mask(A, 1, C, D) -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,clwb,pcommit") #include <wmmintrin.h> #include <smmintrin.h> #include <mm3dnow.h> -- 1.8.3.1
