This patch to the AArch64 back end adds a couple of additional bics
patterns to match code of the form
if ((x & y) == x) ...;
This is testing whether the bits set in x are a subset of the bits set
in y; or, that no bits in x are set that are not set in y. So, it is
equivalent to
if ((x & ~y) == 0) ...;
Presently this generates code like
and x21, x21, x20
cmp x21, x20
b.eq c0 <main+0xc0>
and this patch allows it to be written more concisely as:
bics x21, x20, x21
b.eq c0 <main+0xc0>
Since the bics instruction sets the condition codes itself, no explicit
comparison is required and the result of the bics computation can be
discarded.
Regression-tested on aarch64-linux-gnu. OK to commit?
-Sandra
2014-11-12 Sandra Loosemore <san...@codesourcery.com>
Chris Jones <chr...@nvidia.com>
gcc/
* config/aarch64/aarch64.md (*and<mode>3_compare_op1): New.
(*and<mode>3_compare_op2): New.
gcc/testsuite/
* gcc.target/aarch64/bics_3.c: New.
Index: gcc/config/aarch64/aarch64.md
===================================================================
--- gcc/config/aarch64/aarch64.md (revision 217322)
+++ gcc/config/aarch64/aarch64.md (working copy)
@@ -2894,6 +2894,32 @@
[(set_attr "type" "logics_shift_imm")]
)
+;; ((a & b) == a) ==> ((a & ~b) == 0)
+(define_insn "*and<mode>3_compare_op1"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC
+ (and:GPI (match_operand:GPI 1 "register_operand" "r")
+ (match_operand:GPI 2 "register_operand" "r"))
+ (match_dup 1)))
+ (clobber (match_scratch:GPI 0 "=r"))]
+ ""
+ "bics\\t%<w>0, %<w>1, %<w>2"
+ [(set_attr "type" "logics_reg")]
+)
+
+;; ((a & b) == b) ==> ((b & ~a) == 0)
+(define_insn "*and<mode>3_compare_op2"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC
+ (and:GPI (match_operand:GPI 1 "register_operand" "r")
+ (match_operand:GPI 2 "register_operand" "r"))
+ (match_dup 2)))
+ (clobber (match_scratch:GPI 0 "=r"))]
+ ""
+ "bics\\t%<w>0, %<w>2, %<w>1"
+ [(set_attr "type" "logics_reg")]
+)
+
(define_insn "clz<mode>2"
[(set (match_operand:GPI 0 "register_operand" "=r")
(clz:GPI (match_operand:GPI 1 "register_operand" "r")))]
Index: gcc/testsuite/gcc.target/aarch64/bics_3.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/bics_3.c (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/bics_3.c (revision 0)
@@ -0,0 +1,87 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+bics_si_test1 (int a, int b, int c)
+{
+ if ((a & b) == a)
+ return a;
+ else
+ return c;
+}
+
+int
+bics_si_test2 (int a, int b, int c)
+{
+ if ((a & b) == b)
+ return b;
+ else
+ return c;
+}
+
+typedef long long s64;
+
+s64
+bics_di_test1 (s64 a, s64 b, s64 c)
+{
+ if ((a & b) == a)
+ return a;
+ else
+ return c;
+}
+
+s64
+bics_di_test2 (s64 a, s64 b, s64 c)
+{
+ if ((a & b) == b)
+ return b;
+ else
+ return c;
+}
+
+int
+main ()
+{
+ int x;
+ s64 y;
+
+ x = bics_si_test1 (0xf00d, 0xf11f, 0);
+ if (x != 0xf00d)
+ abort ();
+
+ x = bics_si_test1 (0xf11f, 0xf00d, 0);
+ if (x != 0)
+ abort ();
+
+ x = bics_si_test2 (0xf00d, 0xf11f, 0);
+ if (x != 0)
+ abort ();
+
+ x = bics_si_test2 (0xf11f, 0xf00d, 0);
+ if (x != 0xf00d)
+ abort ();
+
+ y = bics_di_test1 (0x10001000f00dll, 0x12341000f00dll, 0ll);
+ if (y != 0x10001000f00dll)
+ abort ();
+
+ y = bics_di_test1 (0x12341000f00dll, 0x10001000f00dll, 0ll);
+ if (y != 0)
+ abort ();
+
+ y = bics_di_test2 (0x10001000f00dll, 0x12341000f00dll, 0ll);
+ if (y != 0)
+ abort ();
+
+ y = bics_di_test2 (0x12341000f00dll, 0x10001000f00dll, 0ll);
+ if (y != 0x10001000f00dll)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+/* { dg-final { cleanup-saved-temps } } */
