Hi! This patch prevents conditional loads/stores to be added into interleaved groups (where it ICEs later on).
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk/4.9? 2014-10-21 Jakub Jelinek <ja...@redhat.com> PR tree-optimization/63563 * tree-vect-data-refs.c (vect_analyze_data_ref_accesses): Bail out if either dra or drb stmts are not normal loads/stores. * gcc.target/i386/pr63563.c: New test. --- gcc/tree-vect-data-refs.c.jj 2014-10-03 10:10:42.000000000 +0200 +++ gcc/tree-vect-data-refs.c 2014-10-20 15:21:47.938679992 +0200 @@ -2551,11 +2551,14 @@ vect_analyze_data_ref_accesses (loop_vec over them. The we can just skip ahead to the next DR here. */ /* Check that the data-refs have same first location (except init) - and they are both either store or load (not load and store). */ + and they are both either store or load (not load and store, + not masked loads or stores). */ if (DR_IS_READ (dra) != DR_IS_READ (drb) || !operand_equal_p (DR_BASE_ADDRESS (dra), DR_BASE_ADDRESS (drb), 0) - || !dr_equal_offsets_p (dra, drb)) + || !dr_equal_offsets_p (dra, drb) + || !gimple_assign_single_p (DR_STMT (dra)) + || !gimple_assign_single_p (DR_STMT (drb))) break; /* Check that the data-refs have the same constant size and step. */ --- gcc/testsuite/gcc.target/i386/pr63563.c.jj 2014-10-20 15:27:17.713745577 +0200 +++ gcc/testsuite/gcc.target/i386/pr63563.c 2014-10-20 15:27:57.637023020 +0200 @@ -0,0 +1,17 @@ +/* PR tree-optimization/63563 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx2" } */ + +struct A { unsigned long a, b, c, d; } a[1024] = { { 0, 1, 2, 3 } }, b; + +void +foo (void) +{ + int i; + for (i = 0; i < 1024; i++) + { + a[i].a = a[i].b = a[i].c = b.c; + if (a[i].d) + a[i].d = b.d; + } +} Jakub