On Fri, Sep 26, 2014 at 12:45 PM, Kirill Yukhin <kirill.yuk...@gmail.com> wrote:
> Hello,
> Patch in the bottom adds support for vptest[n]m, ucmp, cmpeq.
>
> Bootstrapped.
> AVX-512* tests on top of patch-set all pass
> under simulator.
>
> Is it ok for trunk?
>
> gcc/
> * config/i386/i386.c
> (ix86_expand_args_builtin): Handle CODE_FOR_avx512vl_cmpv4di3_mask,
> CODE_FOR_avx512vl_cmpv8si3_mask, CODE_FOR_avx512vl_ucmpv4di3_mask,
> CODE_FOR_avx512vl_ucmpv8si3_mask, CODE_FOR_avx512vl_cmpv2di3_mask,
> CODE_FOR_avx512vl_cmpv4si3_mask, CODE_FOR_avx512vl_ucmpv2di3_mask,
> CODE_FOR_avx512vl_ucmpv4si3_mask.
> * config/i386/sse.md
> (define_insn
Double "define_insn" here.
> (define_insn "avx512f_ucmp<mode>3<mask_scalar_merge_name>"): Delete.
> "<avx512>_ucmp<VI12_AVX512VL:mode>3<mask_scalar_merge_name>"):New.
> (define_insn
> "<avx512>_ucmp<VI48_AVX512VL:mode>3<mask_scalar_merge_name>"):Ditto.
> (define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"): Ditto.
> (define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"): Ditto.
> (define_insn "<avx512>_gt<mode>3<mask_scalar_merge_name>"): Ditto.
> (define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"): Ditto.
> (define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"): Ditto.
OK.
Thanks,
Uros.
> --
> Thanks, K
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 1aec70f..352ab81 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -34062,6 +34062,14 @@ ix86_expand_args_builtin (const struct
> builtin_description *d,
> case CODE_FOR_avx512f_cmpv16si3_mask:
> case CODE_FOR_avx512f_ucmpv8di3_mask:
> case CODE_FOR_avx512f_ucmpv16si3_mask:
> + case CODE_FOR_avx512vl_cmpv4di3_mask:
> + case CODE_FOR_avx512vl_cmpv8si3_mask:
> + case CODE_FOR_avx512vl_ucmpv4di3_mask:
> + case CODE_FOR_avx512vl_ucmpv8si3_mask:
> + case CODE_FOR_avx512vl_cmpv2di3_mask:
> + case CODE_FOR_avx512vl_cmpv4si3_mask:
> + case CODE_FOR_avx512vl_ucmpv2di3_mask:
> + case CODE_FOR_avx512vl_ucmpv4si3_mask:
> error ("the last argument must be a 3-bit immediate");
> return const0_rtx;
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index e52d40c..625a2e0 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -2517,11 +2517,25 @@
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
>
> -(define_insn "avx512f_ucmp<mode>3<mask_scalar_merge_name>"
> +(define_insn "<avx512>_ucmp<mode>3<mask_scalar_merge_name>"
> [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
> (unspec:<avx512fmaskmode>
> - [(match_operand:VI48_512 1 "register_operand" "v")
> - (match_operand:VI48_512 2 "nonimmediate_operand" "vm")
> + [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
> + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")
> + (match_operand:SI 3 "const_0_to_7_operand" "n")]
> + UNSPEC_UNSIGNED_PCMP))]
> + "TARGET_AVX512BW"
> + "vpcmpu<ssemodesuffix>\t{%3, %2, %1,
> %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2, %3}"
> + [(set_attr "type" "ssecmp")
> + (set_attr "length_immediate" "1")
> + (set_attr "prefix" "evex")
> + (set_attr "mode" "<sseinsnmode>")])
> +
> +(define_insn "<avx512>_ucmp<mode>3<mask_scalar_merge_name>"
> + [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
> + (unspec:<avx512fmaskmode>
> + [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
> + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")
> (match_operand:SI 3 "const_0_to_7_operand" "n")]
> UNSPEC_UNSIGNED_PCMP))]
> "TARGET_AVX512F"
> @@ -10265,20 +10279,42 @@
> (set_attr "prefix" "vex")
> (set_attr "mode" "OI")])
>
> -(define_expand "avx512f_eq<mode>3<mask_scalar_merge_name>"
> +(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
> + [(set (match_operand:<avx512fmaskmode> 0 "register_operand")
> + (unspec:<avx512fmaskmode>
> + [(match_operand:VI12_AVX512VL 1 "register_operand")
> + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")]
> + UNSPEC_MASKED_EQ))]
> + "TARGET_AVX512BW"
> + "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
> +
> +(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
> [(set (match_operand:<avx512fmaskmode> 0 "register_operand")
> (unspec:<avx512fmaskmode>
> - [(match_operand:VI48_512 1 "register_operand")
> - (match_operand:VI48_512 2 "nonimmediate_operand")]
> + [(match_operand:VI48_AVX512VL 1 "register_operand")
> + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")]
> UNSPEC_MASKED_EQ))]
> "TARGET_AVX512F"
> "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
>
> -(define_insn "avx512f_eq<mode>3<mask_scalar_merge_name>_1"
> +(define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
> [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
> (unspec:<avx512fmaskmode>
> - [(match_operand:VI48_512 1 "register_operand" "%v")
> - (match_operand:VI48_512 2 "nonimmediate_operand" "vm")]
> + [(match_operand:VI12_AVX512VL 1 "register_operand" "%v")
> + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
> + UNSPEC_MASKED_EQ))]
> + "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
> + "vpcmpeq<ssemodesuffix>\t{%2, %1,
> %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
> + [(set_attr "type" "ssecmp")
> + (set_attr "prefix_extra" "1")
> + (set_attr "prefix" "evex")
> + (set_attr "mode" "<sseinsnmode>")])
> +
> +(define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
> + [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
> + (unspec:<avx512fmaskmode>
> + [(match_operand:VI48_AVX512VL 1 "register_operand" "%v")
> + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
> UNSPEC_MASKED_EQ))]
> "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
> "vpcmpeq<ssemodesuffix>\t{%2, %1,
> %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
> @@ -10361,11 +10397,11 @@
> (set_attr "prefix" "vex")
> (set_attr "mode" "OI")])
>
> -(define_insn "avx512f_gt<mode>3<mask_scalar_merge_name>"
> +(define_insn "<avx512>_gt<mode>3<mask_scalar_merge_name>"
> [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
> (unspec:<avx512fmaskmode>
> - [(match_operand:VI48_512 1 "register_operand" "v")
> - (match_operand:VI48_512 2 "nonimmediate_operand" "vm")]
> UNSPEC_MASKED_GT))]
> + [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
> + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
> UNSPEC_MASKED_GT))]
> "TARGET_AVX512F"
> "vpcmpgt<ssemodesuffix>\t{%2, %1,
> %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
> [(set_attr "type" "ssecmp")
> @@ -10373,6 +10409,18 @@
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
>
> +(define_insn "<avx512>_gt<mode>3<mask_scalar_merge_name>"
> + [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
> + (unspec:<avx512fmaskmode>
> + [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
> + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
> UNSPEC_MASKED_GT))]
> + "TARGET_AVX512BW"
> + "vpcmpgt<ssemodesuffix>\t{%2, %1,
> %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
> + [(set_attr "type" "ssecmp")
> + (set_attr "prefix_extra" "1")
> + (set_attr "prefix" "evex")
> + (set_attr "mode" "<sseinsnmode>")])
> +
> (define_insn "sse2_gt<mode>3"
> [(set (match_operand:VI124_128 0 "register_operand" "=x,x")
> (gt:VI124_128
> @@ -10818,22 +10866,44 @@
> ]
> (const_string "<sseinsnmode>")))])
>
> -(define_insn "avx512f_testm<mode>3<mask_scalar_merge_name>"
> +(define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"
> [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
> (unspec:<avx512fmaskmode>
> - [(match_operand:VI48_512 1 "register_operand" "v")
> - (match_operand:VI48_512 2 "nonimmediate_operand" "vm")]
> + [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
> + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
> + UNSPEC_TESTM))]
> + "TARGET_AVX512BW"
> + "vptestm<ssemodesuffix>\t{%2, %1,
> %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
> + [(set_attr "prefix" "evex")
> + (set_attr "mode" "<sseinsnmode>")])
> +
> +(define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"
> + [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
> + (unspec:<avx512fmaskmode>
> + [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
> + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
> UNSPEC_TESTM))]
> "TARGET_AVX512F"
> "vptestm<ssemodesuffix>\t{%2, %1,
> %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
> [(set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
>
> -(define_insn "avx512f_testnm<mode>3<mask_scalar_merge_name>"
> +(define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"
> + [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
> + (unspec:<avx512fmaskmode>
> + [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
> + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
> + UNSPEC_TESTNM))]
> + "TARGET_AVX512BW"
> + "vptestnm<ssemodesuffix>\t{%2, %1,
> %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
> + [(set_attr "prefix" "evex")
> + (set_attr "mode" "<sseinsnmode>")])
> +
> +(define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"
> [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
> (unspec:<avx512fmaskmode>
> - [(match_operand:VI48_512 1 "register_operand" "v")
> - (match_operand:VI48_512 2 "nonimmediate_operand" "vm")]
> + [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
> + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
> UNSPEC_TESTNM))]
> "TARGET_AVX512F"
> "vptestnm<ssemodesuffix>\t{%2, %1,
> %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
