On Mon, Sep 22, 2014 at 5:35 PM, Michael Meissner <meiss...@linux.vnet.ibm.com> wrote: > I was working to support enhancing addressing modes in the the compiler that > is > indended to better support load fusion in power8, and to finally allow > DFmode/SFmode scalar values in the traditional altivec registers. I noticed > that the floating point moves were still using constraints that could target > registers that a mode isn't allowed to occupy. This has been an issue with > LRA > in the past. In addition, I noticed the boolean ops for TImode in VSX > register > also used the general wa constraint instead of the wt constraint. > > I have done a bootstrap with these changes and had no regressions. Are the > patches ok to install? > > 2014-09-22 Michael Meissner <meiss...@linux.vnet.ibm.com> > > * config/rs6000/rs6000.md (f32_vsx): New mode attributes to > refine the constraints used on 32/64-bit floating point moves. > (f32_av): Likewise. > (f64_vsx): Likewise. > (f64_dm): Likewise. > (f64_av): Likewise. > (BOOL_REGS_OUTPUT): Use wt constraint for TImode instead of wa. > (BOOL_REGS_OP1): Likewise. > (BOOL_REGS_OP2): Likewise. > (BOOL_REGS_UNARY): Likewise. > (mov<mode>_hardfloat, SFmode/SDmode): Tighten down constraints for > 32/64-bit floating point moves. Do not use wa, instead use ww/ws > for moves involving VSX registers. Do not use constraints that > target VSX registers for decimal types. > (mov<mode>_hardfloat32, DFmode/DDmode): Likewise. > (mov<mode>_hardfloat64, DFmode/DDmode): Likewise.
Okay. Thanks, David
