On Thu, Aug 14, 2014 at 1:30 PM, Kirill Yukhin <kirill.yuk...@gmail.com> wrote: > Hello, > This patch extends load/store insns. > No built-ins added in this patch. > > Bootstrapped. > New tests on top of patch-set all pass > under simulator. > > Is it ok for trunk? > > gcc/ > * config/i386/i386.c > (ix86_expand_special_args_builtin): Handle avx512vl_storev8sf_mask, > avx512vl_storev8si_mask, avx512vl_storev4df_mask, > avx512vl_storev4di_mask, > avx512vl_storev4sf_mask, avx512vl_storev4si_mask, > avx512vl_storev2df_mask, > avx512vl_storev2di_mask, avx512vl_loadv8sf_mask, > avx512vl_loadv8si_mask, > avx512vl_loadv4df_mask, avx512vl_loadv4di_mask, > avx512vl_loadv4sf_mask, > avx512vl_loadv4si_mask, avx512vl_loadv2df_mask, > avx512vl_loadv2di_mask, > avx512bw_loadv64qi_mask, avx512vl_loadv32qi_mask, > avx512vl_loadv16qi_mask, > avx512bw_loadv32hi_mask, avx512vl_loadv16hi_mask, > avx512vl_loadv8hi_mask. > * config/i386/i386.md: Allow V32HI mode.
Please update the above entry. > * config/i386/sse.md > (define_mode_iterator VMOVE): Allow V4TI mode. > (define_mode_iterator V_AVX512VL): New. > (define_mode_iterator V): New handling for AVX512VL. > (define_insn "avx512f_load<mode>_mask"): Delete. > (define_insn "<avx512>_load<mode>_mask"): New. > (define_insn "avx512f_store<mode>_mask"): Delete. > (define_insn "<avx512>_store<mode>_mask"): New. > > -- > Thanks, K > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c > index 183b7be..da01ac6 100644 > --- a/gcc/config/i386/i386.c > +++ b/gcc/config/i386/i386.c > @@ -34722,6 +34722,14 @@ ix86_expand_special_args_builtin (const struct > builtin_description *d, > case CODE_FOR_avx512f_storev16si_mask: > case CODE_FOR_avx512f_storev8df_mask: > case CODE_FOR_avx512f_storev8di_mask: > + case CODE_FOR_avx512vl_storev8sf_mask: > + case CODE_FOR_avx512vl_storev8si_mask: > + case CODE_FOR_avx512vl_storev4df_mask: > + case CODE_FOR_avx512vl_storev4di_mask: > + case CODE_FOR_avx512vl_storev4sf_mask: > + case CODE_FOR_avx512vl_storev4si_mask: > + case CODE_FOR_avx512vl_storev2df_mask: > + case CODE_FOR_avx512vl_storev2di_mask: > aligned_mem = true; > break; > default: > @@ -34765,6 +34773,20 @@ ix86_expand_special_args_builtin (const struct > builtin_description *d, > case CODE_FOR_avx512f_loadv16si_mask: > case CODE_FOR_avx512f_loadv8df_mask: > case CODE_FOR_avx512f_loadv8di_mask: > + case CODE_FOR_avx512vl_loadv8sf_mask: > + case CODE_FOR_avx512vl_loadv8si_mask: > + case CODE_FOR_avx512vl_loadv4df_mask: > + case CODE_FOR_avx512vl_loadv4di_mask: > + case CODE_FOR_avx512vl_loadv4sf_mask: > + case CODE_FOR_avx512vl_loadv4si_mask: > + case CODE_FOR_avx512vl_loadv2df_mask: > + case CODE_FOR_avx512vl_loadv2di_mask: > + case CODE_FOR_avx512bw_loadv64qi_mask: > + case CODE_FOR_avx512vl_loadv32qi_mask: > + case CODE_FOR_avx512vl_loadv16qi_mask: > + case CODE_FOR_avx512bw_loadv32hi_mask: > + case CODE_FOR_avx512vl_loadv16hi_mask: > + case CODE_FOR_avx512vl_loadv8hi_mask: > aligned_mem = true; > break; > default: > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index a72c206..b8ce6c0 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -1054,7 +1054,7 @@ > (V4SF "ps") (V2DF "pd") > (V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q") > (V32QI "b") (V16HI "w") (V8SI "d") (V4DI "q") > - (V64QI "b") (V16SI "d") (V8DI "q")]) > + (V64QI "b") (V32HI "w") (V16SI "d") (V8DI "q")]) > > ;; SSE vector suffix for floating point modes > (define_mode_attr ssevecmodesuffix [(SF "ps") (DF "pd")]) > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 89a1842..910b29b 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -146,10 +146,21 @@ > (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI > (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI > (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI > - (V2TI "TARGET_AVX") V1TI > + (V4TI "TARGET_AVX") (V2TI "TARGET_AVX") V1TI Are you sure TARGET_AVX is the correct condition for V4TI? > (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF > (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF]) > > +;; All AVX512VL vector modes > +(define_mode_iterator V_AVX512VL > + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL && TARGET_AVX512BW") > + (V16QI "TARGET_AVX512VL && TARGET_AVX512BW") > + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512VL && TARGET_AVX512BW") Is the above && OK? So, you have to pass -m...vl and -m...bw to the compiler to enable these modes? Uros.
